index generation functions logic synthesis for pattern
play

Index Generation Functions: Logic Synthesis for Pattern Matching - PowerPoint PPT Presentation

Jan 09, 2024 •135 likes •524 views

Index Generation Functions: Logic Synthesis for Pattern Matching Tsutomu Sasao Meiji University, Kanagawa, Japan 2015/12/10 2015/12/10 Sasao EPFL2015 1 1 1

  1. Index Generation Functions: Logic Synthesis for Pattern Matching Tsutomu Sasao Meiji University, Kanagawa, Japan 2015/12/10 2015/12/10 Sasao EPFL2015 1 1 1

  2. ��������������������������������� ������������������������������������� . 0110000100010000101001100001000100001010 0101111101101010001101011111011010100011 1111010101110111000011110101011101110001 0001111000010001011100011110000100010111 0011110000000100010100111100000001000101 0111001001000100100101110010010001001001 0010001110001111001000100011100011110010 1111111111010001111000100011100011110010 1110111000110001011011101110001100010110 1010000110100100001110100001101001000011 2015/12/10 2015/12/10 Sasao EPFL2015 2 2

  3. Circuit y1 x1 x2 y2 y3 y4 x40 2015/12/10 2015/12/10 Sasao EPFL2015 3 3

  4. Methods 1. Use a look up table. 2. Convert the table into Verilog code and use logic synthesis tool to generate an FPGA. 3. Use Xilinx CAM IP core. 4. Use a new method. 2015/12/10 2015/12/10 Sasao EPFL2015 4 4

  5. New Method 1. To distinguish 10 vectors, 5 bits are sufficient, in most cases. 2. Find 5 bits to distinguish 10 vectors. 3. Given an input vector, check if there exist a vector that matches the 5 bits. 4. If such a vector exists, check if other bits of the vector are equal to the input. 2015/12/10 2015/12/10 Sasao EPFL2015 5 5

  6. We have 10 vectors of 40 bits. Design a circuit for pattern matching . 0110000100010000101001100001000100001010 0101111101101010001101011111011010100011 1111010101110111000011110101011101110001 0001111000010001011100011110000100010111 0011110000000100010100111100000001000101 0111001001000100100101110010010001001001 0010001110001111001000100011100011110010 1111111111010001111000100011100011110010 1110111000110001011011101110001100010110 1010000110100100001110100001101001000011 2015/12/10 2015/12/10 Sasao EPFL2015 6 6

  7. Index Generation Unit (IGU) Index Generation Unit (IGU) � � X 1 5 � Linear Main AND Circuit Memory AUX X 2 Memory 35 35 X 2 Comparator 35 2015/12/10 2015/12/10 Sasao EPFL2015 7 7 7

  8. Incompletely Specified Index Incompletely Specified Index Generation Function Generation Function f : D { 1 , 2 ,..., k }, → n where D B , B { 0 , 1 } . ⊆ = 2015/12/10 2015/12/10 Sasao EPFL2015 8 8 8

  9. Number of Variables to Represent Number of Variables to Represent Incompletely Specified Index Incompletely Specified Index Generation Functions Generation Functions 2015/12/10 2015/12/10 Sasao EPFL2015 9 9 9

  10. Index Generation Function x1 x2 x3 x4 x5 x6 x7 index 1 � � � � � � � � � � 2 � � � � � � � � ��� 3 � � � � � � � 4 � � � � � � � ���������� 5 � � � � � � � ��������������� 6 � � � � � � � ��� 7 � � � � � � � ������������� 8 � � � � � � � ������� 9 � � � � � � � 10 � � � � � � � 2015/12/10 2015/12/10 Sasao EPFL2015 10 10

  11. 7- -Segment to BCD Converter Segment to BCD Converter 7 7segments BCD a a b c d e f g f b g 1 � � � � � � � e c 2 � � � � � � � 3 � � � � � � � d 4 � � � � � � � ����������������� 5 � � � � � � � ���������������� 6 � � � � � � � ������������� 7 � � � � � � � ������� � 8 � � � � � � � 9 � � � � � � � 10 � � � � � � � 2015/12/10 2015/12/10 Sasao EPFL2015 11 11 11

  12. Q: Which Segments are Necessary? a f b g c e d 2015/12/10 2015/12/10 Sasao EPFL2015 12 12 12

  13. Five Segments are Necessary � {a, a,b b,e, ,e,f f,g ,g} } { 2015/12/10 2015/12/10 Sasao EPFL2015 13 13 13

  14. How many variables, on the average, How many variables, on the average, are necessary to represent are necessary to represent incompletely specified index incompletely specified index generation functions with 7 variables generation functions with 7 variables and weight 10? and weight 10? 2015/12/10 2015/12/10 Sasao EPFL2015 14 14 14

  15. ����������������������������������������������� ������������������������� ��� Number of Functions ��� ��� ��� ��� ��� � � � � ������������������� 978 functions 22 functions 22 functions 2015/12/10 2015/12/10 Sasao EPFL2015 15 15 15

  16. Property Property To represent an incompletely specified index generation function with weight � � 3 k, variables are 2 log ( k 1 ) + − 2 sufficient , f or most cases, when k 7 . ≥ Example: When k =127. � � 2 log ( k 1 ) 3 2 7 3 11 + − = × − = 2 2015/12/10 2015/12/10 Sasao EPFL2015 16 16 16

  17. If each column has at most one non- -zero zero If each column has at most one non element in a decomposition chart, then f f element in a decomposition chart, then can be represented with only the column can be represented with only the column x . variables . variables 1 3 1 x 4 4 2 x 3 x 2 2015/12/10 2015/12/10 Sasao EPFL2015 17 17 17

  18. f 1 x x 4 x x 3 x x 2 x x = ⋅ ∨ ⋅ ∨ ⋅ ∨ ⋅ 2 1 2 1 2 1 2 1 x 1 1 4 3 2 1 4 3 2 x 4 1 4 3 2 x 3 4 3 2 1 x 2 2015/12/10 2015/12/10 Sasao EPFL2015 18 18 18

  19. ��������������������������������� ������������������������ x 1 2 1 4 x 4 x 3 3 x 2 2015/12/10 2015/12/10 Sasao EPFL2015 19 19

  20. If the element 4 is moved right two squares , then f is represented by only x 1 and x 2 x 1 2 � x 4 4 4 x 3 3 x 2 2015/12/10 2015/12/10 Sasao EPFL2015 20 20

  21. A linear transformation permutes elements. y 1 y x x = ⊕ 2 1 1 1 4 y x x = ⊕ 4 4 x 2 2 4 4 y x = 3 3 x 3 y x = 3 4 4 y 2 2015/12/10 2015/12/10 Sasao EPFL2015 21 21

  22. In this case, each column has at most one non-zero element. y 1 y x x = ⊕ 1 1 1 4 2 y x x = ⊕ 4 x 2 2 4 4 y x = 3 3 x 3 y x = 3 4 4 y 2 2015/12/10 2015/12/10 Sasao EPFL2015 22 22

  23. Linear Decomposition Linear Decomposition � � q log ( k 1 ) = + 2 p n q Linear General X Function Function Cost: np Cost: q2 p 2015/12/10 2015/12/10 Sasao EPFL2015 23 23 23

  24. Compound Variables Compound Variables •‣ General form: y a x a x a n x � = ⊕ ⊕ ⊕ 1 1 2 2 n a { 0 , 1 } ∈ i •‣ Compound degree: The number of coefficients with a i =1 . •‣ A variable with the compound degree 1 is primitive . 2015/12/10 2015/12/10 Sasao EPFL2015 24 24 24

  25. Linear Circuits Linear Circuits n MUX n + y = x MUX y x x = ⊕ MUX 1 i 1 1 i 1 j 1 n n n MUX y = x + y x x MUX = ⊕ p ip p ip jp MUX n Compound degree 1 Compound degree 2 2015/12/10 2015/12/10 Sasao EPFL2015 25 25 25

  26. 1- -out out- -of of- -7 code to Index Converter 7 code to Index Converter 1 1-out-of-7 code Index x 7 x 6 x 5 x 4 x 3 x 2 x 1 ����������� ����������� 0 0 0 0 0 0 1 1 �������������� �������������� 2 0 0 0 0 0 1 0 ���������� ���������� ������������� ������������� 0 0 0 0 1 0 0 3 ���� ���� 0 0 0 1 0 0 0 4 ��������� ��������� 0 0 1 0 0 0 0 5 0 1 0 0 0 0 0 6 7 1 0 0 0 0 0 0 2015/12/10 2015/12/10 Sasao EPFL2015 26 26 26

  27. Distribution is Skewed Distribution is Skewed 1-out-of-7 code Index •‣ For each x i , there is x 7 x 6 x 5 x 4 x 3 x 2 x 1 single 1, and 6 0’‚s. 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 2 0 0 0 0 1 0 0 3 0 0 0 1 0 0 0 4 5 0 0 1 0 0 0 0 0 1 0 0 0 0 0 6 1 0 0 0 0 0 0 7 2015/12/10 2015/12/10 Sasao EPFL2015 27 27 27

  28. Only Three Variables are Only Three Variables are Necessary. Necessary. y x x x x = ⊕ ⊕ ⊕ 1 1 3 5 7 y x x x x = ⊕ ⊕ ⊕ 2 2 3 6 7 y x x x x = ⊕ ⊕ ⊕ 3 4 5 6 7 2015/12/10 2015/12/10 Sasao EPFL2015 28 28 28

Recommend

Why Again Logic Synthesis Giovanni De Micheli Why again logic synthesis? Strong

Why Again Logic Synthesis Giovanni De Micheli Why again logic synthesis? Strong

Why Again Logic Synthesis Giovanni De Micheli Why again logic synthesis? Strong intellectual value associated with logic synthesis and optimization Problems are far from being solved Current methods and tools grew out of control

372 views • 24 slides
Synthesis of Ranking Functions and Synthesis of Inductive Invariants and Synthesis of

Synthesis of Ranking Functions and Synthesis of Inductive Invariants and Synthesis of

Synthesis of Ranking Functions and Synthesis of Inductive Invariants and Synthesis of Recurrence Sets via Constraint Solving Andreas Podelski January 17, 2012 1 Program Verification and Constraints Reasoning about program

422 views • 28 slides
Logic Synthesis Overview Design flow Principles of logic synthesis Logic

Logic Synthesis Overview Design flow Principles of logic synthesis Logic

Logic Synthesis Overview Design flow Principles of logic synthesis Logic Synthesis with the common tools Conclusions 2 System Design Flow Electronic System Level (ESL) flow System C TLM, Verification, Profiling

1.12k views • 28 slides
Logic Synthesis Page 1 Introduction to Digital VLSI Logic Synthesis Course Outline Design

Logic Synthesis Page 1 Introduction to Digital VLSI Logic Synthesis Course Outline Design

Introduction to Digital VLSI Logic Synthesis Logic Synthesis Page 1 Introduction to Digital VLSI Logic Synthesis Course Outline Design Compiler Overview Some Words about Physical Compiler Coding Styles Partitioning

986 views • 56 slides
Synthesis and optimization of domino logic Min Zhao and Sachin Sapatnekar Department of

Synthesis and optimization of domino logic Min Zhao and Sachin Sapatnekar Department of

Synthesis and optimization of domino logic Min Zhao and Sachin Sapatnekar Department of Electrical Engineering University of Minnesota Minneapolis, MN 55455 1 Outline I Introduction to domino logic I Domino logic synthesis flow I Technology

231 views • 20 slides
Lecture 25 Built-In Self-Testing Pattern Generation and Response Pattern Generation and Response

Lecture 25 Built-In Self-Testing Pattern Generation and Response Pattern Generation and Response

Lecture 25 Built-In Self-Testing Pattern Generation and Response Pattern Generation and Response Compaction Motivation and economics Definitions Definitions Built-in self-testing (BIST) process BIST pattern generation (PG)

535 views • 50 slides
in Logic Synthesis and their Industrial Contributions Masahiro Fujita VLSI Design and Education

in Logic Synthesis and their Industrial Contributions Masahiro Fujita VLSI Design and Education

Basic and Advanced Researches in Logic Synthesis and their Industrial Contributions Masahiro Fujita VLSI Design and Education Center University of Tokyo 2 Outline Logic synthesis flow Automatic process except for complication

830 views • 62 slides
Logic Programming 1 Logic Programming Instead of using functions as in imperative and

Logic Programming 1 Logic Programming Instead of using functions as in imperative and

Logic Programming 1 Logic Programming Instead of using functions as in imperative and functional programs We use predicates, as in predicate calculus Interpretation = proving theorems 2 Prolog Developed at Univ. of

663 views • 7 slides
Logic synthesis for post-CMOS technologies Eleonora Testa Integrated Systems Laboratory EPFL,

Logic synthesis for post-CMOS technologies Eleonora Testa Integrated Systems Laboratory EPFL,

Logic synthesis for post-CMOS technologies Eleonora Testa Integrated Systems Laboratory EPFL, Lausanne, Switzerland Joint work with Mathias Soeken and Giovanni De Micheli February, 2017 Logic synthesis HDL module function ( Translate a,

578 views • 23 slides
Text-to-Image Generation Yu Cheng Text-to-Image Synthesis Text-to-Image Synthesis

Text-to-Image Generation Yu Cheng Text-to-Image Synthesis Text-to-Image Synthesis

Text-to-Image Generation Yu Cheng Text-to-Image Synthesis Text-to-Image Synthesis StackGAN, AttnGAN, TAGAN, ObjGAN Text-to-Video Synthesis GAN-based methods, VAE-based methods, StoryGAN Dialogue-based Image Synthesis

827 views • 45 slides
A template-based approach for speech synthesis intonation generation using LSTMs Srikanth Ronanki

A template-based approach for speech synthesis intonation generation using LSTMs Srikanth Ronanki

A template-based approach for speech synthesis intonation generation using LSTMs Srikanth Ronanki Gustav Zhizheng Simon Introduction: Statistical speech synthesis SPSS: Generation based approaches Vocoder MGC BAP Regression Text

502 views • 20 slides
VHDL for Logic Synthesis Overview Design Flow for Hardware Design VHDL coding for

VHDL for Logic Synthesis Overview Design Flow for Hardware Design VHDL coding for

VHDL for Logic Synthesis Overview Design Flow for Hardware Design VHDL coding for synthesis General guidelines for hardware designers This lecture includes the content from: Nitin Yogi, Modelling for Synthesis with VHDL, Auburn

697 views • 52 slides
1 Mux Representation of Boolean Functions MUX circuit to implement logic 1 0 x1 x2 x3

1 Mux Representation of Boolean Functions MUX circuit to implement logic 1 0 x1 x2 x3

ECE 474A/57A Computer-Aided Logic Design Lecture 11 Binary Decision Diagrams (BDDs) ECE 474a/575a 1 of 31 Susan Lysecky Boolean Logic Functions Representations Function can be represented in different ways Truth table, equation, K-map,

457 views • 12 slides
La y out-Driven Logic Synthesis Based on Lattices Singapur, Septemb er 1997 1 ' $ LA

La y out-Driven Logic Synthesis Based on Lattices Singapur, Septemb er 1997 1 ' $ LA

La y out-Driven Logic Synthesis Based on Lattices Singapur, Septemb er 1997 1 ' $ LA YOUT-DRIVEN SYNTHESIS F OR SUBMICRON TECHNOLOGY: MAPPING EXP ANSIONS TO REGULAR LA TTICES Ma rek A. P erk o wski, Edmund

634 views • 37 slides
An Approach to Synthesis of An Approach to Synthesis of Multiple-Valued Reversible

An Approach to Synthesis of An Approach to Synthesis of Multiple-Valued Reversible

An Approach to Synthesis of An Approach to Synthesis of Multiple-Valued Reversible Multiple-Valued Reversible Logic Circuits Logic Circuits Pawel Kerntopf Institute of Computer Science Warsaw University of Technology Warsaw, Poland 6th

414 views • 15 slides
Functions How to make the person run? (See: runForest.cpp) Functions You can also use functions

Functions How to make the person run? (See: runForest.cpp) Functions You can also use functions

Functions How to make the person run? (See: runForest.cpp) Functions You can also use functions that return bool types in an if statement or loop This is commonly used if you have complex logic as it is normally easier to write a function

260 views • 10 slides
Brakelock The new frame lock generation March 28th 2018 Synthesis BRAKELOCK is a new generation

Brakelock The new frame lock generation March 28th 2018 Synthesis BRAKELOCK is a new generation

Brakelock The new frame lock generation March 28th 2018 Synthesis BRAKELOCK is a new generation of frame lock. Thanks to a device braking powerfully the rear wheel of the bike , instead of blocking it by a rod passing through like on traditional

564 views • 19 slides
SOME NUMERICAL FUNCTIONS ASSOCIATED TO THE MASLOV INDEX Andrew Ranicki (Edinburgh)

SOME NUMERICAL FUNCTIONS ASSOCIATED TO THE MASLOV INDEX Andrew Ranicki (Edinburgh)

1 SOME NUMERICAL FUNCTIONS ASSOCIATED TO THE MASLOV INDEX Andrew Ranicki (Edinburgh) http://www.maths.ed.ac.uk/ aar The Many Facets of the Maslov Index American Institute of Mathematics, Palo Alto 11th April, 2014 2 Introduction Want

768 views • 38 slides
Logic for Computer Science 07 Functions Wouter Swierstra University of Utrecht 1 Last time

Logic for Computer Science 07 Functions Wouter Swierstra University of Utrecht 1 Last time

Logic for Computer Science 07 Functions Wouter Swierstra University of Utrecht 1 Last time Proof strategies 2 Today Functions 3 Functions Given two sets A and B, we can form a new set A B consisting of functions from A to B.

908 views • 63 slides
Logic Synthesis in the Twilight of Moores Law Near-threshold, Heterogeneous, 3D Design Looking

Logic Synthesis in the Twilight of Moores Law Near-threshold, Heterogeneous, 3D Design Looking

Logic Synthesis in the Twilight of Moores Law Near-threshold, Heterogeneous, 3D Design Looking for a New Toolbox Luca Benini IIS-ETHZ & DEI-UNIBO IoT: a System View Sense Analyze and Classify Transmit MEMS IMU Short range, BW

282 views • 25 slides
Probabilistic and Logistic Circuits: A New Synthesis of Logic and Machine Learning Guy Van den

Probabilistic and Logistic Circuits: A New Synthesis of Logic and Machine Learning Guy Van den

Probabilistic and Logistic Circuits: A New Synthesis of Logic and Machine Learning Guy Van den Broeck RelationalAI ArrowCon Feb 5, 2019 Which method to choose? Classical AI Methods: Neural Networks: Hungry $25? ? Restaura Sleep? nt?

819 views • 56 slides
Conditional Program Generation for Bimodal Program Synthesis Swarat Chaudhuri Rice University

Conditional Program Generation for Bimodal Program Synthesis Swarat Chaudhuri Rice University

Conditional Program Generation for Bimodal Program Synthesis Swarat Chaudhuri Rice University www.cs.rice.edu/~swarat (Joint work with Chris Jermaine, Vijay Murali, and Letao Qi) Program synthesis [Simon 1963, Summers 1977, Manna-Waldinger

411 views • 22 slides
Correlation via Synthesis: End-to-end Image Generation and Radiogenomic Learning Based on

Correlation via Synthesis: End-to-end Image Generation and Radiogenomic Learning Based on

Correlation via Synthesis: End-to-end Image Generation and Radiogenomic Learning Based on Generative Adversarial Network Ziyue Xu, Senior Scientist | MIDL 2020 PURPOSE, METHOD, & LIMITATION What to Expect Goal: looking for the

684 views • 19 slides
Synthesis Challenges for Next- Synthesis Challenges for Next- Generation High-Performance and

Synthesis Challenges for Next- Synthesis Challenges for Next- Generation High-Performance and

Synthesis Challenges for Next- Synthesis Challenges for Next- Generation High-Performance and Generation High-Performance and High-Density PLDs High-Density PLDs Jason Cong Songjie Xu Jason Cong Songjie Xu Department of Computer Science

959 views • 59 slides

More recommend