Grokking FPGA clock management Philmon Gardet Jean-Franois - PowerPoint PPT Presentation

Grokking FPGA clock management Philémon Gardet Jean-François Nguyen <phil@lse.epita.fr> <jf@lse.epita.fr>

Architecture 2

Architecture Overview ● IO buffers ● PLLs / DLLs ● CLBs ● Interconnect ● Block RAM 3

CLB - Configurable Logic Blocks ● Logic Cell: LUT, carry logic, storage ● Chained carry ● Fast adjacent interconnect ● clk signal 4

PLL & DLL Input clock Phase-locked loop Delay-locked loop 5

Clock Networking ● Fan-out Clock signal intensity ● Clock skew Different phases from the same source 6

Clock Networking - Clock Tree ● Global networks Regional Low-skew / High fanout ● Regional networks Global Mid-skew / Mid fanout ● Edge networks Low-skew / high speed / IO 7

Clock Tree Strategy 8

Timing considerations 9

Clock Skew clk clk1 D Q D Q D Q clk2 clk1 clk2 clk3 clk3 clk Clock skew 10

Short Path clk d q1 q2 d D Q D Q q1 clk q2 11

Short Path clk clk1 clk2 d q1 q2 D Q D Q clk1 clk2 d clk q1 q2 12

Short Path - Fixes Clock reversing d q1 q2 D Q D Q ● Add delay in data path clk1 clk2 ● Clock Reversing clk Alternate Phase clocking d q1 q2 ● Alternate Phase Clocking D Q D Q DLL ○ clk1 clk2 ○ Differents edge triggers Clock buffering ○ clk1 clk2 13

Place and Route ● Routability ○ Avoid coupling capacitance or detours ● Timing constraints ○ Bound delay on each path ● Power consumption ● Yield 14

Timing Analysis ● Minimum clock period is dictated by the largest delay ● Slack is the tolerated delay before increasing the minimum clock period Critical path has a slack of 0 ● 15

Asynchronous & others dumb things 16

Metastability D Q a c ● Real world b ⟶ transitive time a ● Intermediate logic state b ● Unknown behaviour if output feeds data to another stage c 17

Combinatory Logic as Trigger - Short paths b a ● Without any synchronization no hypothesis about order q c ● Metastability possibility d 18

Latches - Race condition ● Asynchronous control ● Transitive state Combinatory Combinatory D Q logic logic E ● Loop ⟶ No idea about a current state 19

Combinatory Logic - Delay blocks b a delay ● Force delay on each input delay q c delay ● Control transitive state delay d 20

Handshaking pipeline Req delay Ack Sender Receiver Data path Delay to send req signal = worst data setting time 21

Asynchronous data encoding protocols - dual rail Ack d r value r0 0 0 Null d0 1 0 1 Sender Receiver r1 0 1 0 d1 1 1 Invalid Double the data bus → Assure validity 22

Manual Place & Route ● No depend to place & route algorithms changes ● Control clock skew and delays ● Automatization optimized for asynchronous logic ? 23

Thank you! 24

Bibliography ● FPGA Architecture, timing, software / Mose Wahlstrom - Lattice R&D Team, 2013 ● The real hardware / V. Angeloc - VHDL-FPGA@PI, 2013 7 Series FPGAs Clocking Resources User Guide / Lattice, 2017 ● ● iCE40 LP/HX Family Data Sheet / Lattice, 2017 Routing Algorithms and Architectures for Field-Programmable Gate arrays / ● Stephen Dean Brown, 1992 Design Guidelines for Optimal Results in High-Density FPGAs / Altera, 2003 ● ● Rapid System Prototyping with FPGAs / R.C. Coffer, Ben Harding - Elsevier, 2005 ● Application of Specific Delay Window Routing for Timing Optimization in FPGA Designs / Evan Wegley, Qinhai Zhag - Lattice, 2015 ● Clock Skew and Short Paths Timing / Microsemi, 2011 The Art of hardware architecture / Mohit Arora - Springer, 2012 ● 25