The World Leader in High-Performance Signal Processing Solutions Clock IC Product Update Clock IC Product Update Clock Distribution and Clock Generation Solutions Clock Distribution and Clock Generation Solutions September 2005 September 2005
Dimensions of Clock and Timing ICs Obvious Obvious Not so Obvious Not so Obvious Speed Speed Channel Isolation Channel Isolation Edge Skew Edge Skew RF Interference RF Interference Jitter Jitter Slew Rate Slew Rate Phase Noise Phase Noise Design Tools Design Tools Synchronization Synchronization Line Terminations Line Terminations External Oscillators External Oscillators 2
ADI Clock IC Innovations for Cost Design Tools Design Tools Before you even step Before you even step foot into the lab… … foot into the lab - design clock circuit design clock circuit - - select components select components - - test ideas test ideas - - check performance - check performance … … save time and money save time and money Clean Interfaces, Ease of Use Clean Interfaces, Ease of Use Small Packages Small Packages Differential LVPECL for Differential LVPECL for 32 LFCSP 32 LFCSP chip- -to to- -chip signals. chip signals. chip 5mm x 5mm 5mm x 5mm AD9513/14/15 have AD9513/14/15 have Saves board Saves board pin- -programmable programmable pin space space divides, phase, delay… divides, phase, delay … no serial port required no serial port required 3
Signal- -to to- -Noise Ratio in Data Converters Noise Ratio in Data Converters Signal 4
Digital ADC Output Analog Input SNR Sampling Clock Why ADI must advance performance clocks Clock Jitter/Phase Noise can reduce SNR in data converters Digital DAC Input Analog Output (after LPF) SNR Sampling Clock 5 www.analog.com/clocks
ADCs perform great in the lab… Ain=165 MHz Encode=80 MSPS SNR=71.78 dB 6 layer board 2 signal 2 ground 2 power Good Clock Source Jitter ~0.15 ps 6 www.analog.com/clocks
…but in a real application! Ain=165 MHz Encode=80 MSPS SNR=58.88 dB 6 layer board 2 signal 2 ground 2 power Typical Gate, High Speed CMOS Jitter ~0.8 ps 7 www.analog.com/clocks
Jitter – A common noise source introduced at the SHA in A-D Converter � Clock jitter is the sample to sample variation in the encode clock (both the external jitter as well as the internal jitter). � Fullscale SNR is jitter limited by: dV S 1 = = SNR 20 log rms 20 log error voltage jitter π N 2 ft rms jitter � See AN-501 and new AN-756 Encode SHA = Sample & Hold Amplifier SNR = Signal to Noise Ratio 8 www.analog.com/clocks
Looking for RMS clock jitter in 0.1-2ps range 130 RMS Jitter < 1ps is very high performance 120 .125 pS .25 pS 110 .5 pS 1 pS 16 bits 100 2 pS SNR in dB 90 14 bits 80 12 bits 70 10 bits 60 50 Want to use ADI data converters here 40 Analog Freq 70-300MHz, SNR 60-80dB 30 1 10 100 1000 Input in MHz 9 www.analog.com/clocks
Clock Products in production Primary Voltage Max Input Max Random Clock Supply Frequency Output Jitter Part# On-Chip No. of Output I/O Package Function (V) (MHz) Frequency Multiplier Outputs Logic (ps rms) Interface (MHz) LVPECL 0.25 additive AD9510 Distribution PLL Core +3.3V 1600 8 1200 LVDS Serial 64 LFCSP CMOS LVPECL 0.25 additive AD9511 Distribution PLL Core +3.3V 1600 5 1200 LVDS Serial 48 LFCSP CMOS LVPECL 0.25 additive AD9512 Distribution No +3.3V 1600 5 1200 LVDS Serial 48 LFCSP CMOS LVDS 0.3 Pin additive Select AD9513 Distribution No +3.3V 1600 3 800 CMOS 32 LFCSP LVPECL 0.225 Pin additive Select AD9514 Distribution No +3.3V 1600 3 1600 LVDS 32 LFCSP CMOS LVPECL 0.225 Pin additive Select AD9515 Distribution No +3.3V 1600 2 1600 LVDS 32 LFCSP CMOS CML +1.8V & AD9540 Generation PLL Core 655 2 655 0.7 total Serial 48 LFCSP +3.3V Analog 10
AD9516 AD9516 11
Clock ICs with on-chip VCOs VS GND RSET CPRSET VCP ADI Clock ICs continue to ADI Clock ICs continue to AD9516 DIST REF CHECK LOR PLL REFIN integrate high value functions to integrate high value functions to REF CHECK DLD PFD REFIN PROGRAMMABLE R DIVIDER "R" DELAY REFINB PHASE CHARGE lower system cost: lower system cost: FREQUENCY CP N DIVIDER PUMP DET ECT OR P, P+1 A/B PROGRAMMABLE PRESCALER COUNT ERS "N" DELAY CHECK INT ERNAL STA TUS LEVELS • complete PLL w/on complete PLL w/on- -chip VCO chip VCO • OSC VIN OUT LINEAR L F BUFFER CLK1 DIVIDE BY • 5 programmable dividers 5 programmable dividers LOW DROPOUT • BYPA SS 2,3,4,5, or 6 CLK1B REGULAT OR (LDO) OUT0 • 4 programmable delay lines 4 programmable delay lines DIVIDERS w/PHASE OFFSET • OUT0B POWER PDB DOWN DIVIDE BY 1 T O 32 LVPECL OUT1 • 10 clock outputs synchronized • 10 clock outputs synchronized SYNCB, FUNCTION RESET B OUT1B to input reference to input reference OUT2 SCLK SERIAL OUT2B SDIO CONT ROL SDO PORT DIVIDE BY 1 T O 32 LVPECL CSB (Default) OUT3 OUT3B OUT4 OUT4B DIVIDE BY 1 T O 32 LVPECL DELAY OUT5 OUT5B ADJUST OUT6 ∆ T OUT6B LVDS/CMOS DIVIDE BY 1 T O 32 DIVIDE BY 1 T O 32 OUT7 ∆ T OUT7B OUT8 ∆ T OUT8B Featured in block diagram, AD9516, is in Featured in block diagram, AD9516, is in LVDS/CMOS DIVIDE BY 1 T O 32 DIVIDE BY 1 T O 32 OUT9 development now with samples in Feb. 06 development now with samples in Feb. 06 ∆ T OUT9B 12
AD9516 Summary 1.6GHz Clock Distribution IC with on-chip VCO � Low noise PLL with on-chip VCO In Development Now In Development Now � Low Jitter Clock Distribution Samples Feb. ‘ ‘06 06 Samples Feb. � Low Skew Clock Outputs � 10 Clock Outputs � Six LVPECL at 1.6GHz � Four LVDS/CMOS at 800/250MHz � Programmable Dividers � Programmable Phase Offset � Four Fine Delay Adjust Elements � 64 LFCSP Package pin-similar to AD9510 � -40 ° C to +85 ° C operation � 3.3V Core supply � LVPECL Outputs 2.5V, 3.3V compatible 13 www.analog.com/clocks
ADI in Clock Distribution ADC Clock to A-D Converters ADC ADC ADC AD9510 User’s Reference Clock Distribution IC DDC or Clock ASIC Clock to Digital Chips DUC or ADI Clock Distribution ICs lower overall ADI Clock Distribution ICs lower overall FPGA system noise: system noise: • clocks with sub clocks with sub- -picosecond jitter picosecond jitter • DAC • best best- -in in- -class channel isolation class channel isolation • Clock to D-A Converters • clean clean- -up jitter on user up jitter on user’ ’s input reference s input reference • DAC 14
ADI clock ICs simplify board ADI clock ICs simplify board QUADRATURE TRANSMIT SOURCE QUADRATURE TRANSMIT SOURCE design by integrating phase design by integrating phase 61.44 MHz 61.44 MHz control, delay adjust, frequency control, delay adjust, frequency PHASE = 90 ° PHASE = 90 ° CMOS CMOS dividers and logic translation dividers and logic translation DAC DAC PHASE = 0 ° PHASE = 0 ° 122.88 122.88 61.44 MHz 61.44 MHz DELAY = 10ns DELAY = 10ns MHz MHz LVDS LVDS CMOS CMOS 30.72 MHz 30.72 MHz FPGA DAC FPGA DAC REFCLK REFCLK 491.52 MHz 491.52 MHz LOOP LOOP LVPECL LVPECL FILTER FILTER 30.72 MHz 30.72 MHz CLEAN_REFCLK CLEAN_REFCLK HIGH PRECISION MEASUREMENT SUBSYSTEM HIGH PRECISION MEASUREMENT SUBSYSTEM VCXO VCXO CALIBRATION CALIBRATION LVPECL LVPECL 15.36 MHz 15.36 MHz TOYOCOM TOYOCOM 491.52 491.52 491.52 MHz 491.52 MHz ADC FIFO ADC FIFO LVPECL CMOS LVPECL CMOS 122.88 MHz 122.88 MHz 122.88 MHz 122.88 MHz DELAY = 4.3ns DELAY = 4.3ns 15
ADI in Clock Generation ADI Clock Generation ICs combine low jitter, with fine ADI Clock Generation ICs combine low jitter, with fine phase and frequency control. The output clocks may phase and frequency control. The output clocks may be programmed to 1 part in 2 48 resulting in micro- -Hertz Hertz be programmed to 1 part in 2 48 resulting in micro frequency resolution. frequency resolution. Frequency = 622.08 MHz Clock Path A Synchronize to AD9540 User reference clock Clock Generation IC Frequency = 38.88 MHz or Use fixed 25MHz crystal Clock Path B Clock Generation ICs have multiple configuration options to lock two different frequencies to a single reference, while maintaining low jitter and precise synchronization 16
Combine clock generation with clock distribution for a complete timing solution Low Jitter Frequency Source Output may be synchronized to external reference. LF Reference AD9540 AD9512 or DC to 655 MHz Cystal ADI Clock ICs offer designers a complete ADI Clock ICs offer designers a complete Combine with AD9512 solution: solution: Clock Distribution chip for • Precise Clock Generation Precise Clock Generation • 5 Output Clocks Programmable • Low Jitter Clock Distribution Low Jitter Clock Distribution • Divide Ratio, Phase Select and Delay Adjust • Optimized interface between timing ICs Optimized interface between timing ICs • 17
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