George J. Starr Jie Qin Bradley F. Dutton Charles E. Stroud F. Foster Dai Victor P. Nelson 1
�������� � Goals � Model Design � Top Level Architecture � Program Program � VHDL Generation � Example Implementations � Experimental Results � Summary 2
����� � Perform on chip calculations of: � Linearity � Frequency Response � Noise Figure � Noise Figure Built-In Self-Test BIST 3
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������������������������ � TableEntry= A*sin(3.141592* I / (2*B) ) � A is the magnitude of the output ○ A=2 #of magnitude bits -1 � B is the number of entries in the table � B is the number of entries in the table B -1 ○ B=#of table entries � I is the table index value A 6
������������ case table_index is when 0 => table_value := 0; when 1 => table_value := 1304; table_value := 1304; when 2 => table_value := 2401; when 3 => table_value := 3001; ……… 7
��������������� ���� A Sin 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 0 0 -0.8 -1 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 A Cos 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 0 -0.8 -1 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 8
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$%������&��������������� Mux ADC R _ DUT + C DAC R R R C FPGA C TPG ORA R R R 12
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����������(���������� 0dB -10dB 25dB 40dB -20dB -30dB -40dB -50dB -60dB -70dB 2*F1-F2 F1 F2 2*F2-F1 14
��������� 25dB rength (dB) 80dB Signal Stren Frequency (Hz) Frequency (Hz) Very Non-Linear System Linear System 15
)��*������'��������+ ���� dB) Gain (dB Frequency (Hz) 16
)��*������'��������+,���� ans) 0 Degrees Phase (radian -90 Degrees Frequency (Hz) 17
������)����� SNR 10 * log ( ) ( ) = = − NoiseFigur e SNR db SNR db in in out SNR out SNR IN = 109dB SNR OUT = 81dB NF = 28dB 81dB (dB) Signal Strength (d RunTime=0.52s Frequency (Hz) 18
������� � Capability to measure � Linearity � Frequency Response � Noise Figure � Automatic Generation of VHDL Automatic Generation of VHDL � Overcome lack of VHDL trigonometric functions � Implementation in any mixed-signal system ○ FPGA and ASIC � Fast & accurate measurements compared to external test equipment 19
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