Built- -In Self In Self- -Test for Programmable Test for Programmable Built I/O Buffers in FPGAs FPGAs and and SoCs SoCs I/O Buffers in Sudheer Vemula and Charles Stroud Sudheer Vemula and Charles Stroud Electrical and Computer Engineering Electrical and Computer Engineering Auburn University Auburn University presented at 2006 IEEE Southeastern Symp Symp. On . On presented at 2006 IEEE Southeastern System Theory System Theory 3/22/2006 VLSI Design & Test Seminar Series
Outline of Presentation Outline of Presentation � Motivation and Background Motivation and Background � � Overview of programmable I/O buffers Overview of programmable I/O buffers � Built- -In Self In Self- -Test Architecture Test Architecture � Built � � Results Retrieval and Diagnosis Results Retrieval and Diagnosis � � Embedded Processor Based BIST Embedded Processor Based BIST � � Experimental Results Experimental Results � � Atmel AT94K series Atmel AT94K series SoC SoC � � Xilinx Virtex Xilinx Virtex- -4 series 4 series FPGAs FPGAs � Summary � Summary � 3/22/2006 VLSI Design & Test Seminar Series
Programmable I/O Buffers Programmable I/O Buffers � Programmable I/O buffer can be: Programmable I/O buffer can be: � Boundary Boundary � Input, Output, Bi Input, Output, Bi- -directional directional � Scan Scan � Package connections Package connections Tri- -state Control state Control Tri � Access Access � Bonded or Bonded or unbonded unbonded � � Different types (some FPGAs) Different types (some FPGAs) � to/from internal to/from internal Output Data Output Data � Primary, Secondary, Clock Primary, Secondary, Clock � programmable programmable � Programmable resources Programmable resources � routing resources routing resources PAD PAD � Logic Logic � Input Data Input Data � Multiplexers, flip Multiplexers, flip- -flops, latches flops, latches � � Virtex � Virtex- -4: 32 4: 32 MUXs MUXs & 10 & 10 FFs FFs � Active levels Active levels � Y Y Y Y � Enables, set/reset, clocks Enables, set/reset, clocks � X X X X X X X X CLB CLB CLB CLB Y Y Y Y Y Y � Pull Pull- -up, pull up, pull- -down, keeper down, keeper Y Y � X X X X X X X X Y Y Y Y � Drive capabilities Drive capabilities � � Delays, slew rate Delays, slew rate � I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O � I/O voltage standards (Virtex I/O voltage standards (Virtex- -4: 69) 4: 69) � � Routing resources to/from Routing resources to/from � = primary I/O = secondary I/O = primary I/O = secondary I/O buffer buffer buffer buffer FPGA core FPGA core 3/22/2006 VLSI Design & Test Seminar Series
Motivation and Background Motivation and Background � Need to test programmable I/O buffers in Need to test programmable I/O buffers in � FPGAs to insure proper system operation to insure proper system operation FPGAs � Boundary Scan lacks access to all resources Boundary Scan lacks access to all resources � in programmable I/O buffers in programmable I/O buffers � Configurable Configurable SoCs SoCs often incorporate often incorporate � programmable I/O buffers for FPGA cores programmable I/O buffers for FPGA cores � FPGA synthesis tools often use resources FPGA synthesis tools often use resources � in unbonded unbonded I/O buffers for system function I/O buffers for system function in Prior work in Built- -In Self In Self- -Test for Test for FPGAs FPGAs � Prior work in Built � � BIST for internal logic and routing resources BIST for internal logic and routing resources � � No BIST for programmable I/O buffers No BIST for programmable I/O buffers � 3/22/2006 VLSI Design & Test Seminar Series
Increase in Resources in I/O Buffers Increase in Resources in I/O Buffers No. of No. of Max. No. of I/O Max. No. of I/O FPGA/Soc Year FPGA/Soc Year Registers per Registers per Buffers Buffers I/O Buffer I/O Buffer ATMEL ATMEL 0 1999 0 1999 384 (AT40K40) 384 (AT40K40) AT40(10)K AT40(10)K ATMEL ATMEL 2 2002 2 2002 256 (AT94S40) 256 (AT94S40) AT94K AT94K XILINX XILINX 3 2002 3 2002 512 (XCV1000) 512 (XCV1000) VIRTEX VIRTEX 3 3 2002 2002 XILINX VIRTEX E XILINX VIRTEX E 804 (XCV3200E) 804 (XCV3200E) 1164 1164 XILINX XILINX 6 2003 6 2003 (XC2VP70/100/ (XC2VP70/100/ VIRTEX II PRO VIRTEX II PRO XC2VPX70) XC2VPX70) 784 784 XILINX XILINX 6 6 2005 2005 SPARTAN3 SPARTAN3 (XC3S5000) (XC3S5000) 960 960 10 2005 10 2005 XILINX VIRTEX 4 XILINX VIRTEX 4 (XC4VLX200) (XC4VLX200) 3/22/2006 VLSI Design & Test Seminar Series
I/O Buffer BIST Architecture I/O Buffer BIST Architecture � Configure bi Configure bi- -directional buffer under test (BUT) directional buffer under test (BUT) � � Output response analyzer (ORA) comparison Output response analyzer (ORA) comparison- -based based � � Latches mismatches due to faults in BUT Latches mismatches due to faults in BUT � � Output of BUT compared by 2 Output of BUT compared by 2 ORAs ORAs with 2 other with 2 other BUTs BUTs � � Test pattern generator (TPG) = counter or LFSR Test pattern generator (TPG) = counter or LFSR � � Implemented in FPGA Configurable Logic Blocks ( Implemented in FPGA Configurable Logic Blocks (CLBs CLBs) ) � � Multiple Multiple TPGs TPGs prevent prevent CLBs CLBs faults from masking IOB faults from masking IOB � faults faults =TPG =ORA 3/22/2006 VLSI Design & Test Seminar Series
I/O Buffer BIST Architecture I/O Buffer BIST Architecture � Test patterns applied to all possible inputs to I/O Test patterns applied to all possible inputs to I/O � buffers to test routing resources buffers to test routing resources � Multiple BIST configurations needed to completely Multiple BIST configurations needed to completely � test I/O buffer in all modes of operation test I/O buffer in all modes of operation from TPG to ORA Programmable Programmable Routing Resources Routing Resources 3/22/2006 VLSI Design & Test Seminar Series
ORA Designs ORA Designs � Comparator Comparator- -based design based design � � feedback & flip feedback & flip- -flop latch any flop latch any � mismatch due to faults in Buffers mismatch due to faults in Buffers Under Test (BUTs BUTs) ) Under Test ( LUT � ORA results retrieval ORA results retrieval � Outputs � Integrated ORA and scan chain Integrated ORA and scan chain � From LUT BUTs � More logic for scan chain More logic for scan chain � Shift In � Interface to Boundary Scan Interface to Boundary Scan � Shift � Configuration memory Configuration memory readback readback � � No added logic for scan chain No added logic for scan chain � Outputs � Partial configuration memory Partial configuration memory readback readback � from � Readback Readback from embedded processor from embedded processor � LUT BUTs � Diagnosis performed by embedded Diagnosis performed by embedded � processor processor 3/22/2006 VLSI Design & Test Seminar Series
Circular Comparison Diagnosis Circular Comparison Diagnosis Step 1: Record ORA results Record ORA results Step 1: Step 2: Mark all Buffers Under Test ( Mark all Buffers Under Test (BUTs BUTs) associated with ) associated with Step 2: two or more consecutive ORAs with 0s (0=fault- -free) free) two or more consecutive ORAs with 0s (0=fault Step 3: Recursively mark Recursively mark BUTs BUTs with 1 (1=faulty) for every with 1 (1=faulty) for every Step 3: consecutive 0 and 1 followed by empty cell consecutive 0 and 1 followed by empty cell Step 4: Inconsistencies mean fault in BUT Inconsistencies mean fault in BUT- -to to- -ORA routing ORA routing Step 4: resources or in ORAs ORAs if they have not been tested and if they have not been tested and resources or in known to be fault- -free free known to be fault Step 5: Unique diagnosis if all Unique diagnosis if all BUTs BUTs marked faulty or fault marked faulty or fault- -free free Step 5: Note: buffers B3 and B4 have equivalent faults Note: buffers B3 and B4 have equivalent faults O 91 O 91 O 91 B 1 B 1 B 1 O 12 O 12 O 12 B 2 B 2 B 2 O 23 O 23 B 3 O 23 B 3 B 3 O 34 O 34 O 34 B 4 B 4 B 4 O 45 O 45 O 45 B 5 B 5 B 5 O 56 O 56 O 56 B 6 B 6 B 6 O 67 O 67 O 67 B 7 B 7 B 7 O 78 O 78 O 78 B 8 B 8 B 8 O 89 O 89 O 89 B 9 B 9 B 9 O 91 O 91 O 91 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 3/22/2006 VLSI Design & Test Seminar Series
Embedded Processor Based BIST Embedded Processor Based BIST � Given access to FPGA configuration Given access to FPGA configuration � memory, an embedded processor can memory, an embedded processor can � Reconfigure I/O buffers in various modes of Reconfigure I/O buffers in various modes of � operation operation � Execute BIST sequence Execute BIST sequence � � Retrieve BIST results from Retrieve BIST results from ORAs ORAs � � Perform diagnosis based on BIST results Perform diagnosis based on BIST results � � Processor can be hard or soft core Processor can be hard or soft core � � Significant improvements in Significant improvements in � Memory for storing BIST configurations � Memory for storing BIST configurations � � Test time Test time � 3/22/2006 VLSI Design & Test Seminar Series
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