AUGUST 2018 Programmable Data Plane at Terabit Speeds Milad Sharif SOFTWARE ENGINEER
PISA: Protocol Independent Switch Architecture
PISA − Block Diagram Match+Action Stage Memory ALU Programmable Programmable Match-Action Pipeline Parser 3
PISA − Match-Action Unit • Multiple simultaneous lookups and actions can be supported Memory ALU ALU Memory Memory ALU Memory ALU ALU Memory Memory ALU Sequential Execution Staggered Execution Parallel Execution (Match dependency) (Action dependency) (No dependency)
Introducing Tofino
6.5Tb/s Tofino TM − Overview Four Match+Action Pipelines MAC + Serial I/O • Fully programmable PISA Embodiment • Single Shared Packet Buffer • 16nm technology Match+Action Match+Action Pipeline 0 Pipeline 1 Shared Packet Port Configurations Buffer + • 260 × 25 SerDes, support 1G, 10G, 25G, 40G, 50G, and 100G ports TM Match+Action Match+Action Pipeline 2 Pipeline 3 CPU Interfaces • PCIe: Gen3 × 4/ × 2/ × 1 • Dedicated 100GE port 6
Tofino − Simplified Block Diagram Reset / Clocks PCIe CPU MAC DMA engines Control & configuration Ingress Egress Rx MACs Tx MAC Pipeline 10/25/40/50/100 Pipeline 10/25/40/50/100 pipe 0 Ingress Egress Rx MACs Tx MAC 10/25/40/50/100 Pipeline Pipeline 10/25/40/50/100 pipe 1 Traffic Manager Ingress Egress Rx MACs Tx MAC Pipeline Pipeline 10/25/40/50/100 10/25/40/50/100 pipe 2 Ingress Egress Rx MACs Tx MAC Pipeline Pipeline 10/25/40/50/100 10/25/40/50/100 pipe 3 7
Fully-Programmable Parser SRAM TCAM Eth. Next state State Data Action Packet Header Vector IPv4 IPv6 Next state Protocol== 0x11 Protocol== 0x06 Match Field Extract Match Field selection UDP TCP shift control Input Shift Register Output Field Extractor From MAC 8
Packet Header Vector (PHV) 8 8-bit words 8 • A set of uniform containers that carry the headers and metadata. along the pipeline 16 • Fields can be packed into any container or their combination. 16-bit words 16 • Packing is decided by PHV Allocation pass in the compiler. 32 32-bit words 32 9
Match − Action Unit Delay × Xbar # Instr. Operand RAM Data Key Instruction PHV Address Match Action RAM/TCAM RAM ALUs: Meters, Statistisc, Stateful
Match − Action Pipeline Full packet Deparser Parser Match Match Match Match Action Action Action Action Unit Unit Unit Unit
Match − Action Pipeline Full packet Deparser IPv4 Parser uRPF ACL IPv6 IPv4 IPv6 • Multiple small tables per stage ACL • Large tables spread over multiple stages
Unified Match − Action Pipeline Combined Ingress/Egress Match-Action Pipeline MAU 0 MAU n PHV PHV MAC Packet Buffers Constructor MAC Queues And Deparser Ingress Ingress Parser Ingress Packet Ingress Buffer MAC MAC Ingress Packet body
Unified Match − Action Pipeline Egress header Egress Packet body Combined Ingress/Egress Match-Action Pipeline MAU 0 MAU n PHV PHV MAC MAC Constructor Deparser Deparser Egress Egress Packet Egress MAC MAC MAC Packet Buffers Constructor Deparser Queues And MAC Ingress Ingress Ingress Parser Packet Ingress Buffer MAC MAC Ingress Packet body
Unified Match − Action Pipeline Egress header Egress Packet body Combined Ingress/Egress Match-Action Pipeline MAU 0 MAU n PHV PHV MAC MAC Constructor Deparser Deparser Egress Egress Packet Egress MAC MAC MAC Packet Buffers Constructor Deparser Queues And MAC Ingress Ingress Ingress Parser Packet Ingress Buffer MAC MAC Recirculation Buffer (Packet Reference, Metadata) Ingress Packet body
Programming Tofino
Tofino Architecture • Data plane interfaces /// Register extern Register<T, I> { /// Instantiate an array of <size> registers. /// The initial value is undefined. Register(bit<32> size); • Intrinsic Metadata /// Initialize an array of <size> registers and set ingress_mac_tstamp − ingress timestamp assigned by MAC /// their value to initial_value. Register(bit<32> size, T initial_value); ucast_egress_port − output port /// Return the value of register at specified index. T read(in I index); • Tofino-specific Extern /// Write value to register at specified index. void write(in I index, in T value); Registers, Counters, Meters, Filters, etc. }
Runtime Configuration User Defined Packet Test P4 16 Core Application Framework Library Fronend P4 BF-Runtime APIs Program Backend BF-Runtime P4 Architecture Model info P4 Compiler ASIC driver Extern Arch. PSA V1Model Libraries Definition Target-Specific Configuration ASIC Model /// Indexed counter with `size’ independent /// counter values. extern Counter<W, I> { /// Constructor /// @type_param W : width of the counter value. Provided by /// @type_param I : width of the counter index. P4 Visualization Barefoot Networks /// @param type : counter type. Packet an byte /// counters are supported. Counter(bit<32> size, CounterType_t type); /// Increment the counter value. /// @param index: index of the counter to be /// incremented. void count(in I index); }
Multi − Pipeline configuration Pipeline Configuration P4 Compiler App1.p4 Extern Arch. P4 16 Core Libraries Definition Library P4 Compiler App2.p4 Pipeline Configuration
Thank You Contact Information MSHARIF@BAREFOOTNETWORKS.COM
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