A Unified Program for Modifying Built-In Self-Test Architectures for Xilinx Field Programmable Gate Arrays Neil Da Cunha Auburn University November 2 nd , 2011 Committee Members: Charles E. Stroud, Chair, Professor of Electrical and Computer Engineering Vishwani D. Agrawal, Professor of Electrical and Computer Engineering Victor P. Nelson, Professor of Electrical and Computer Engineering
Abstract & Problem Statement Abstract A Built-In Self-Test (BIST) session for Xilinx Field Programmable Gate Arrays (FPGAs) is created with two programs. The first program, a BIST generation program, creates a template file which is then modified by the second program, a BIST modification program, into the different phases that make up a test session. Currently there are fifteenth BIST generation programs and fourteen BIST modification programs. Problem Statement To design a unified C program to modify any Field Programmable Gate Array (FPGA) Built-In Self Test (BIST) template file into the collection of different phases needed to properly test the full functionality of a desired component, also called a session.
Overview of FPGAs FPGAs are prefabricated integrated circuits that can implement the functionality of any digital circuit ◮ Configurable Logic Blocks (CLBs)
Overview of FPGAs FPGAs are prefabricated integrated circuits that can implement the functionality of any digital circuit ◮ Configurable Logic Blocks (CLBs) ◮ Programmable Input/Output Buffers (IOBs)
Overview of FPGAs FPGAs are prefabricated integrated circuits that can implement the functionality of any digital circuit ◮ Configurable Logic Blocks (CLBs) ◮ Programmable Input/Output Buffers (IOBs) ◮ Programmable Interconnects
Overview of FPGAs FPGAs are prefabricated integrated circuits that can implement the functionality of any digital circuit ◮ Configurable Logic Blocks (CLBs) ◮ Programmable Input/Output Buffers (IOBs) ◮ Programmable Interconnects ◮ Configuration Memory
Overview of FPGAs FPGAs are prefabricated integrated circuits that can implement the functionality of any digital circuit ◮ Configurable Logic Blocks (CLBs) ◮ Programmable Input/Output Buffers (IOBs) ◮ Programmable Interconnects ◮ Configuration Memory ◮ Optional: Dedicated cores, for example ◮ DSPs (Digital Signal Processors) ◮ RAMs ◮ Power PC microprocessor
Overview of BIST for FPGAs Overview ◮ Basic idea: reprogram FPGA to test itself ◮ No area overhead or performance penalties ◮ Applicable to all levels of testing ◮ Application independent testing
Overview of BIST for FPGAs Overview ◮ Basic idea: reprogram FPGA to test itself ◮ No area overhead or performance penalties ◮ Applicable to all levels of testing ◮ Application independent testing Challenges ◮ External memory to store BIST configuration data for the BIST phases ◮ Goal: minimize number of phase as well as using compressed configuration and partial reconfiguration techniques ◮ Test time = download + execute + results ◮ Dominated by download time ◮ Goal: minimize downloads and/or download time ◮ Results retrieval has the second most impact ◮ Goal: provide Pass/Fail indication (fault detection only) w/o sacrificing diagnostic resolution (fault-tolerant apps)
Overview of BIST for Xilinx FPGAs Three major components ◮ Test Pattern Generators (TPGs) ◮ Block Under Tests (BUTs) ◮ Multiple TPGs are used to avoid fault escape ◮ Output Response Analyzers (ORAs) ◮ Comparison based ◮ Latches “0” due to mismatch ◮ Carry chain performs iterative OR function ◮ Single pass/fail bit ◮ Read configuration memory for diagnosis
Table of BISTs developed for Xilinx FPGAs BIST Types Devices Virtex-4 Virtex-5 Spartan6 CLB 10 6 In Progress LRAM 5 5 - IOLOGIC 5 6 - SERDES 9 10 - DSP 5 11 In Progress BUFG 2 2 - CRC - 2 - BRAM 6 7 In Progress FIFO 5 4 - ECC 2 3 - FIFECC - 2 - CASC - 2 -
XDL - Xilinx Design Language ◮ A netlist format for describing and configuring circuits at the component level ◮ Used to carefully place and configure the BIST circuitry ◮ Meant for internal work at Xilinx, as a result there is no formal documentation ◮ Everything had to be learned by experience or experimentation BAD Syntax GOOD Syntax i n s t ”name” ” type ” , placed loc , i n s t ”name” ” type ” , placed loc , cfg ” lorem ipsum delorem ” cfg ” lorem ipsum delorem ” ; ;
FPGA BIST Flow For a particular device and BIST type 1. A BIST generation program creates a generic, unrouted template in xdl for a particular device and BIST type i n s t ”name” ” type ” , placed loc , cfg ” Lorem ipsum d o l o r s i t ” ; net ”name” , outpin ”comp name” pin , i n p i n ”comp name” pin , i n p i n ”comp name” pin , ;
FPGA BIST Flow For a particular device and BIST type 1. A BIST generation program creates a generic, unrouted template in xdl for a particular device and BIST type 2. The xdl file is converted to an ncd file by the Xilinx xdl program
FPGA BIST Flow For a particular device and BIST type 1. A BIST generation program creates a generic, unrouted template in xdl for a particular device and BIST type 2. The xdl file is converted to an ncd file by the Xilinx xdl program 3. The ncd file is then routed in Xilinx FPGA Editor or using Xilinx par program
FPGA BIST Flow For a particular device and BIST type 1. A BIST generation program creates a generic, unrouted template in xdl for a particular device and BIST type 2. The xdl file is converted to an i n s t ”name” ” type ” , placed loc , cfg ” Lorem ipsum d o l o r s i t ” ncd file by the Xilinx xdl program ; 3. The ncd file is then routed in Xilinx FPGA Editor or using net ”name” , Xilinx par program outpin ”comp name” pin , i n p i n ”comp name” pin , 4. The routed ncd file is converted i n p i n ”comp name” pin , back into an xdl file using Xilinx pip ”name” ”name” − > ”name” , xdl program pip ”name” ”name” − > ”name” , ;
FPGA BIST Flow For a particular device and BIST type 1. A BIST generation program creates a generic, unrouted template in xdl for a particular device and BIST type 2. The xdl file is converted to an i n s t ”name” ” type ” , placed loc , cfg ” Ut enim ad minim ” ncd file by the Xilinx xdl program ; 3. The ncd file is then routed in Xilinx FPGA Editor or using net ”name” , Xilinx par program outpin ”comp name” pin , i n p i n ”comp name” pin , 4. The routed ncd file is converted i n p i n ”comp name” pin , back into an xdl file using Xilinx pip ”name” ”name” − > ”name” , xdl program pip ”name” ”name” − > ”name” , ; 5. This routed XDL file is then configured into the necessary phase for a BIST type by a BIST modification program
FPGA BIST Flow For a particular device and BIST type 1. A BIST generation program creates a generic, unrouted template in xdl for a particular device and BIST type 2. The xdl file is converted to an i n s t ”name” ” type ” , placed loc , cfg ” Ut enim ad minim ” ncd file by the Xilinx xdl program ; 3. The ncd file is then routed in Xilinx FPGA Editor or using net ”name” , Xilinx par program outpin ”comp name” pin , i n p i n ”comp name” pin , 4. The routed ncd file is converted i n p i n ”comp name” pin , back into an xdl file using Xilinx pip ”name” ”name” − > ”name” , xdl program pip ”name” ”name” − > ”name” , ; 5. This routed XDL file is then configured into the necessary phase for a BIST type by a BIST modification program 6. Optionally converted to an ncd or a bit file
BIST Programs in detail BIST generation programs BIST modification programs ◮ Generate the initial BIST ◮ Configures template into template various phases ◮ Specifies the location and ◮ Specifies configuration of interconnections of all BIST BIST components components ◮ One for every device and ◮ One for every device and BIST type except for BUFG BIST type BIST ◮ Share very little code in ◮ Share code and functionality common with each other
Problem Statement Restated Problem Statement “To design a unified C program to modify any Field Programmable Gate Array (FPGA) Built-In Self Test (BIST) template file into the collection of different phases needed to properly test the full functionality of a desired component, also called a session.” Additional Requirements The program must meet the following criteria, in order of importance: 1. Has to describe an identical architecture/circuit 2. Has to be easily extendible 3. Reuse code whenever possible 4. Produce consistently formatted xdl files
Overview of the Program Three main sections to the program 1. Input validation 2. XDL Processing Finite State Machine ◮ Reconfigure components - mainly BUTs ◮ Inverting clocks ◮ Removing nets for certain forms of BIST 3. Post-Processing - optionally outputting an ncd or bit file
XDL Processing Finite State Machine ◮ parse initalized to COPY state
XDL Processing Finite State Machine ◮ parse initalized to COPY state ◮ COPY state checks for keywords and sets parse
XDL Processing Finite State Machine ◮ parse initalized to COPY state ◮ COPY state checks for keywords and sets parse ◮ INST state searches for components depending on BIST type
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