Programable Logic Devices In the 1970s programmable logic circuits called programmable logic device (PLD) was introduced. They are based on a structure with an AND- OR array that makes it easy to implement SOP expression William Sandqvist william@kth.se
PLD structure x 1 x x 2 n Input buffers and inverters x 1 x x n x 1 n P 1 OR plane AND plane P k f f 1 m William Sandqvist william@kth.se
Programmable Logic Array (PLA) x x x 1 2 3 Both AND and OR arrays are OR plane P 1 programmable P 2 P 3 P 4 AND plane f f William Sandqvist william@kth.se
Programmable Array Logic (PAL) x x x 1 2 3 Only the AND array is programmable P 1 f 1 P 2 P 3 f 2 P 4 AND plane William Sandqvist william@kth.se
Register output In the earlier PLD circuits there were • combinatorial outputs • register outputs (output with a flip-flop) For each circuit there were a fixed number of combinational and register outputs To increase flexibility the macrocell where you could choose if an output would be a combinatorial or a register output was introduced. William Sandqvist william@kth.se
Macrocels ia a PLD Select Enable f 1 Flip-flop D Q With a programmable multiplexer one can Clock select the type of output To AND plane William Sandqvist william@kth.se
PAL William Sandqvist william@kth.se
Programing of PLDs William Sandqvist william@kth.se
Complex PLDs (CPLD) PLD were quite small (PALCE 22V10 had 10 flip-flops) For bigger programmable circuits a structure consisting of several PLD-like block was developed. William Sandqvist william@kth.se
CPLD (MAX) William Sandqvist william@kth.se
CPLD structure I/O block I/O block PAL-like PAL-like block block Interconnection wires I/O block I/O block PAL-like PAL-like block block William Sandqvist william@kth.se
Programing with JTAG Modern CPLDs (and FPGAs) can be programmed by downloading programming information via a cable Download will usually use a standard port: JTAG-port William Sandqvist william@kth.se
JTAG programing You can program the chips when they are soldered to the circuit board - from inside the programmer you (a) CPLD in a Quad Flat Pack (QFP) package can select which chip you want to program with the To compute r JTAG connector. P rinte d circuit boa rd (b) JTAG programming William Sandqvist william@kth.se
FPGA chips CPLD :s are based on the AND-OR array, and it becomes difficult to make really large circuits FPGA (Field Programmable Gate Array) circuits using a different concept based on logical blocks William Sandqvist william@kth.se
FPGA-structure William Sandqvist william@kth.se
LUT-LookUp-Table A LUT with n Programmable 0/1 1 cells inputs can realize all combinational 0/1 0 functions with n 1 inputs. f The usual size in 0/1 0 an FPGA is n =4 1 0/1 0 x 2 x 1 Two-input LUT William Sandqvist william@kth.se
Ex. LUT for XOR-gate 0 1 x x f 2 1 1 0 1 1 0 1 f 0 1 1 0 1 1 1 0 1 0 0 0 0 0 x 2 x 1 Two-input LUT William Sandqvist william@kth.se
Logic block in FPGA A logic block of an FPGA consists of a LUT, a flip- flop, and a mux to select register output. Select Out Flip-flop In 1 In D Q LUT 2 In 3 Clock William Sandqvist william@kth.se
Interconnexion matrix in FPGA x f 3 • Blue cross: connection is x 1 programmed • Black cross: x 0 x 0 1 2 0 1 f 1 f 2 0 0 connection is not x x x 2 2 3 1 0 programmed f 1 0 1 f 1 f 2 1 William Sandqvist william@kth.se
DE2 University Board Cyclone II EP2C35 FPGA – Datorteknik- course William Sandqvist william@kth.se
Cyclone II logic element William Sandqvist william@kth.se
Cyclone II Family DE2 (3) Total Number of 18x18 Multipliers William Sandqvist william@kth.se
Stratix III Family DE3 Board William Sandqvist william@kth.se
Multiple processors on an FPGA • Nios II is a so-called 'soft- processor' (32-bit) which can be implemented on an Nios II Altera FPGA • Today's FPGAs are so large that multiple Nios II processors can fit on a single FPGA chip Very powerful multiprocessor systems can be created on an FPGA! William Sandqvist william@kth.se
ASIC • An ASIC (Application Specific Integrated Circuit) is a circuit that is madi in a semiconductor factory • In a full custom integrated circuit you in principle tailors the whole circuit • In an ASIC have certain work steps already been made to reduce design time and cost William Sandqvist william@kth.se
ASIC, gate array In an Gate Array the gates (or transistors) are allready on the silicon. William Sandqvist william@kth.se
ASIC, gate array f 1 One only creates x 1 links between inputs, gates, and x outputs 2 x 3 William Sandqvist william@kth.se
Comparison ASIC, FPGA Initial Cost Cost per part Performance Fabrication Time FPGA Low High Low Short Gate Array (ASIC) Standard Cell High Low High Long (ASIC) William Sandqvist william@kth.se
Design Trade-Offs Design Time Full Custom Standard Cell Gate Array Programmable Logic Microprocessor Performance William Sandqvist william@kth.se
William Sandqvist william@kth.se
Sekvenskretsar med VHDL State NEXT STATE OUTPUT STATE REGISTER DECODER DECODER Input- Output- signals signals Clk Moore-machine William Sandqvist william@kth.se
Model a State Machine in VHDL • In a Moore-machine we have three blocks – Next-state-decoder – Output-decoder – State-register • These blocks execute in parallel William Sandqvist william@kth.se
Quickie Question … which logic gate corresponds to the following VHDL code William Sandqvist william@kth.se
Quickie Question … which logic gate corresponds to the following VHDL code William Sandqvist william@kth.se
Quickie Question … which logic gate corresponds to the following VHDL code William Sandqvist william@kth.se
Quickie Question … which logic gate corresponds to the following VHDL code William Sandqvist william@kth.se
Processes in VHDL • An architecture in VHDL can consist of several processes • Processes are executed in parallel • A process is written as a sequential program William Sandqvist william@kth.se
Moore-machine processes • For a Moore-machine, we can create three processes – Next-state-decoder – Output-decoder – State-register William Sandqvist william@kth.se
Internal signals • Moore-machine contains internal signals – Next state – Present state • Theese signals are declared in the architecture -description William Sandqvist william@kth.se
The vending machine in VHDL We use bottle vending machine (system control) from last lecture as a concrete VHDL example COIN_PRESENT DROP COIN DROP BOTTLE RECEIVER GT_1_EURO DROP_READY SYSTEM EQ_1_EURO CONTROL LT_1_EURO DEC_ACC RETURN_10_CENT COIN RETURN ACCUMU- CLR_ACC CHANGER_READY LATOR William Sandqvist william@kth.se
Vending machine entity ENTITY Vending_Machine IS COIN_PRESENT DROP PORT ( -- Inputs GT_1_EURO DROP_READY coin_present : IN std_logic; SYSTEM EQ_1_EURO gt_1_euro : IN std_logic; CONTROL eq_1_euro : IN std_logic; LT_1_EURO lt_1_euro : IN std_logic; DEC_ACC RETURN_10_CENT drop_ready : IN std_logic; CLR_ACC CHANGER_READY changer_ready : IN std_logic; reset_n : IN std_logic; Reset_n clk : IN std_logic; Clk -- Outputs dec_acc : OUT std_logic; clr_acc : OUT std_logic; Clk and Reset (active low) is drop : OUT std_logic; also needed! return_10_cent : OUT std_logic); END Vending_Machine; William Sandqvist william@kth.se
Vending machine architecture • The architecture describes the function of the vending machine • We define – internal signals for present and next state – three processes for next-state- decoder, output-decoder and state- register William Sandqvist william@kth.se
State diagram (a) Wait for coin input (b) Register the coin (c) Coin is registered (3 cases) (d) Drop bottle (e) Reset sum (f) Return 10 Cent (g) Decrement sum with 10 Cent William Sandqvist william@kth.se
Internal signals • We need to create a data type for the internal signal • Since we describe the states we use an enumeration type with values a,b,c,d,e,f,g • We declare a variable for the current state ( current_state ) and one for next state ( next_state ) ARCHITECTURE Moore_FSM OF Vending_Machine IS TYPE state_type IS (a, b, c, d, e, f, g); SIGNAL current_state, next_state : state_type; BEGIN -- Moore_FSM … William Sandqvist william@kth.se
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