Embedded Processor Based Embedded Processor Based Fault Injection and SEU Fault Injection and SEU Emulation for FPGAs Emulation for FPGAs Bradley Dutton, Mustafa Ali, John Bradley Dutton, Mustafa Ali, John Sunwoo, and Charles Stroud Sunwoo, and Charles Stroud Sunwoo, and Charles Stroud Sunwoo, and Charles Stroud
Outline Outline � � Background Background � � What is Built What is Built-in Self in Self-test for FPGAs? test for FPGAs? � � Example: BIST for Virtex Example: BIST for Virtex-5 Configurable Logic Blocks 5 Configurable Logic Blocks � � Motivation Motivation � � What is FPGA fault emulation? What is FPGA fault emulation? � � Why do we need it? Why do we need it? � � Two case studies of embedded processors used � Two case studies of embedded processors used � Two case studies of embedded processors used Two case studies of embedded processors used for fault injection for fault injection � � Hard processor Hard processor-based fault injection based fault injection � � Atmel AT94K SoC Atmel AT94K SoC � Soft processor � Soft processor-based fault injection and Single based fault injection and Single-Event Event Upset (SEU) emulation Upset (SEU) emulation � � Xilinx Virtex Xilinx Virtex-4 and Virtex 4 and Virtex-5 FPGAs 5 FPGAs � � Conclusions Conclusions 2
BIST for FPGAs BIST for FPGAs � Basic idea: Basic idea: reprogram FPGA to test itself � reprogram FPGA to test itself � � No area overhead or performance penalties No area overhead or performance penalties � � Applicable to all levels of testing Applicable to all levels of testing � Application independent testing � Application independent testing � � A generic test approach for a generic component A generic test approach for a generic component � � Good diagnostic resolution � � Good diagnostic resolution Good diagnostic resolution Good diagnostic resolution � Cost: Cost: � � � Memory to store BIST configurations Memory to store BIST configurations � Goal: Goal: minimize � minimize number and size number and size of configurations of configurations � Test time = download + execute + results � Test time = download + execute + results � � Dominated by download time Dominated by download time � Goal: Goal: minimize downloads and/or download � minimize downloads and/or download time time � Results retrieval is second � Results retrieval is second 3
AUBIST Approach AUBIST Approach � � Configure some logic resources to act as Configure some logic resources to act as � � Test Pattern Generators (TPGs) Test Pattern Generators (TPGs) � � Output Response Analyzers (ORAs) Output Response Analyzers (ORAs) � � Configure other resources to be tested Configure other resources to be tested � � Blocks Under Test (BUTs) Blocks Under Test (BUTs) � � Wires Under Test (WUTs) � � Wires Under Test (WUTs) Wires Under Test (WUTs) Wires Under Test (WUTs) � � For all configurations, maintain constant For all configurations, maintain constant � � placement of TPGs, ORAs, & BUTs placement of TPGs, ORAs, & BUTs � � routing of TPG routing of TPG-to to-BUT & BUT BUT & BUT-to to-ORA ORA � � minimizes download time via partial reconfiguration minimizes download time via partial reconfiguration � � Automatic generation of BIST configurations Automatic generation of BIST configurations � � For any size device in FPGA family For any size device in FPGA family 4
V-5 Configurable Logic Block (CLB) BIST � CLB is most abundant logic resource � 25,920 CLBs in Largest Virtex-5 � 207,360 FFs and 6-input LUTs � 652 configuration bits per CLB � Some CLBs include SliceMs (LUT RAMs) � SliceM can form small RAMs or Shift Register � SliceM can form small RAMs or Shift Register COUT COUT Carry Carry CLB Logic Logic SLICE1 SLICE1 (SliceL) (SliceL) LUT/ LUT/ 6 Switch Switch RAM RAM Matrix Matrix FF/ FF/ (64-bit) (64 bit) SLICE0 SLICE0 Latch Latch (SliceM) (SliceM) 5 CIN CIN
SliceL BIST Architecture SliceL BIST Architecture � � Two test sessions Two test sessions � � East & West East & West � � Every CLB configured as both a Block Under Test Every CLB configured as both a Block Under Test (BUT) and Output Response Analyzer (ORA) (BUT) and Output Response Analyzer (ORA) � Multiple test phases per test session � Multiple test phases per test session � � Test all modes of operation in CLB Test all modes of operation in CLB East East East East East East East East West West West West West West West West TPG TPG TPG TPG TPG TPG TPG TPG BUT BUT ORA ORA TPG TPG 03/17/2009 SSST 6
SliceL BIST Architecture SliceL BIST Architecture � � Test Pattern Generator Test Pattern Generator � � 12 inputs to each basic logic element 12 inputs to each basic logic element � � DSP configured as accumulator generates an exhaustive set DSP configured as accumulator generates an exhaustive set of patterns of patterns � Accumulate prime number 0xCA6691 [1] � Accumulate prime number 0xCA6691 [1] Produces 2 12 patterns in 2 12 12 patterns in 12 clock cycles with high number of � � Produces clock cycles with high number of transitions in most significant bits transitions in most significant bits � � Multiple TPGs connect to alternating columns of BUTs � Multiple TPGs connect to alternating columns of BUTs � Multiple TPGs connect to alternating columns of BUTs Multiple TPGs connect to alternating columns of BUTs � � Eliminates fault Eliminates fault-free TPG assumption free TPG assumption � � Comparison Comparison-based output response analysis based output response analysis � � Compare the outputs of two adjacent, identically configured Compare the outputs of two adjacent, identically configured CLBs CLBs � Row based circular comparison � Row based circular comparison [1] S. Gupta, J. Rajski, and J. Tyszer, “Test pattern generation based on arithmetic operations,” Proc. IEEE Int. Conf. on Computer-Aided Design, pp. 117-124, 1994. 03/17/2009 SSST 7
Iterative Iterative-OR output response analyzer OR output response analyzer � � Each ORA compares two outputs of BUT Each ORA compares two outputs of BUT � � Initialized to logic 1 Initialized to logic 1 � � Any mismatch will latch a logic 0 Any mismatch will latch a logic 0 � � Results retrieved Results retrieved � Partial configuration memory read back � Partial configuration memory read back � � High diagnostic resolution when fault(s) detected High diagnostic resolution when fault(s) detected High diagnostic resolution when fault(s) detected High diagnostic resolution when fault(s) detected � � Via single Via single-bit iterative bit iterative-OR chain output OR chain output ORA k carry-out TDI 0 1 BUT j output x TDO ORA 1 ORA 2 BUT k output x 1 ORA n ORA j carry-out BUT j output y BUT k output y LUT 03/17/2009 SSST 8
SliceM BIST Architecture SliceM BIST Architecture � � Block RAM TPGs store RAM Block RAM TPGs store RAM test vectors test vectors � � March Y + Dual ORA ORA TPG TPG BUT BUT March Y + Dual-port March [2] port March [2] bit BRAM , 8 N = � � 2048 x 18 2048 x 18-bit BRAM , 8 = 8*256 = 2048 vectors 8*256 = 2048 vectors TPG TPG � � Iterative � � Iterative Iterative-OR chain ORA Iterative-OR chain ORA OR chain ORA OR chain ORA � � Column based circular Column based circular comparison comparison TPG TPG � One multiple phase test � One multiple phase test session for all SliceMs session for all SliceMs � � Every CLB with a SLICEM has Every CLB with a SLICEM has a SLICEL for ORA a SLICEL for ORA [2] A. van de Goor, Testing Semiconductor Memories: Theory and Practice , John Wiley and Sons, 1991. 03/17/2009 SSST 9
V-5 SliceL BIST Fault Coverage Single Stuck-at Simulation Single Stuck at Simulation Fault Injection Fault Injection 100 3000 100 600 90 90 2500 Individual FC Individual FC 500 80 80 Cumulative FC # Faults Detected # Faults Detected Cumulative FC 70 70 2000 400 60 60 1500 50 50 300 40 40 1000 200 30 30 20 20 500 100 10 10 0 0 0 0 0 0 0 0 1 2 3 4 5 6 1 2 3 4 5 6 Configuration # Configuration # � Gate-level model (AUSIM) � 3008 gate-level collapsed stuck-at faults � 100% cumulative coverage in 6 phases w/ DSP TPG � Configuration memory fault injection � 614 configuration bit stuck-at faults � 100% cumulative coverage 10
V-5 SliceM BIST Fault Coverage Single Stuck-at Simulation Single Stuck at Simulation Fault Injection Fault Injection 100 100 8000 80 90 90 7000 70 80 80 Individual FC # Faults Detected # Faults Detected 6000 70 60 70 Cumulative FC Individual FC 60 5000 60 50 Cumulative FC 50 50 4000 40 40 40 3000 30 30 30 2000 20 20 20 1000 10 10 10 0 0 0 0 0 0 0 0 1 2 3 4 5 1 2 3 4 5 Configuration # Configuration # � Gate-level model (AUSIM) � 8462 gate-level collapsed stuck-at faults � 100% cumulative coverage in 5 phases w/ RAM tests � Configuration memory fault injection � 85 configuration bit stuck-at faults � 100% cumulative coverage 11
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