Advanced Topics on Heterogeneous System Architectures FPGA Reconfiguration � Politecnico di Milano � Seminar Room, Bld 20 � 4 December, 2017 � Antonio R. Antonio R. Miele Miele � Marco D. Santambrogio Marco D. Santambrogio � Politecnico di Milano �
2 Reconfiguration in everyday life �
3 Reconfiguration in everyday life � Soccer (Par%al – Sta%c)
4 Reconfiguration in everyday life � Football (Complete – Sta%c) Soccer (Par%al – Sta%c)
5 Reconfiguration in everyday life � Football (Complete – Sta%c) Soccer (Par%al – Sta%c) Hockey ) c i m a n y D – l a % r a P (
6 SoC Reconfiguration �
7 SoC Reconfiguration �
8 SoC Reconfiguration �
9 SoC Reconfiguration �
10 SoC Reconfiguration �
11 SoC Reconfiguration � " MANAGER "
12 SoC Reconfiguration � " MANAGER "
13 SoC Reconfiguration � " MANAGER "
14 SoC Reconfiguration � " MANAGER "
15 SoC Reconfiguration � " M A N A G E R "
16 SoC Reconfiguration � " M A N A G E R "
17 SoC Reconfiguration � " M A N A G E R "
18 SoC Reconfiguration � " MANAGER "
19 SoMC Reconfiguration Scenario � • Embedded VS External � • Complete VS Partial � • Dynamic VS Static �
20 SoMC Reconfiguration Scenario � • Embedded VS External � • Complete VS Partial � SYSTEM • Dynamic VS Static � BOARD/FPGAs CARD FPGA FPGA HOST (e.g., PC) FPGA
21 SoMC Reconfiguration Scenario � • Embedded VS External � • Complete VS Partial � SYSTEM • Dynamic VS Static � BOARD/FPGAs CARD FPGA FPGA HOST (e.g., PC) WHO FPGA
22 SoMC Reconfiguration Scenario � • Embedded VS External � • Complete VS Partial � SYSTEM • Dynamic VS Static � BOARD/FPGAs CARD FPGA FPGA WHO HOST (e.g., PC) FPGA
23 SoMC Reconfiguration Scenario � • Embedded VS External � • Complete VS Partial � SYSTEM • Dynamic VS Static � BOARD/FPGAs CARD FPGA FPGA HOST (e.g., PC) FPGA
24 SoMC Reconfiguration Scenario � • Embedded VS External � • Complete VS Partial � • Dynamic VS Static � SYSTEM BOARD/FPGAs CARD FPGA FPGA GA HOST (e.g., PC) FPGA
25 SoMC Reconfiguration Scenario � • Embedded VS External � • Complete VS Partial � • Dynamic VS Static � SYSTEM BOARD/FPGAs CARD FPGA FPGA HOST (e.g., PC) FPGA
26 SoMC Reconfiguration Scenario � • Embedded VS External � • Complete VS Partial � • Dynamic VS Static � SYSTEM BOARD/FPGAs CARD FPGA FPGA HOST (e.g., PC) FPGA
27 SoMC Reconfiguration Scenario � • Embedded VS External � • Complete VS Partial � • Dynamic VS Static � SYSTEM BOARD/FPGAs CARD FPGA FPGA HOST (e.g., PC) FPGA
28 SoMC Reconfiguration Scenario � SYSTEM BOARD/FPGAs CARD FPGA FPGA HOST (e.g., PC) FPGA
29 SoMC Reconfiguration Scenario � SYSTEM BOARD/FPGAs CARD FPGA GA FPGA HOST (e.g., PC) FPGA
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� 31 Some Definitions � • Object Code Object Code: the executable active physical (either HW or SW) implementation of a given functionality � • Core Core: a specific representation of a functionality. It is possible, for example, to have a core described in VHDL, in C or in an intermediate representation (e.g. a DFG) �
� 32 Some Definitions � • Object Code Object Code: the executable active physical (either HW or SW) implementation of a given functionality � • Core Core: a specific representation of a functionality. It is possible, for example, to have a core described in VHDL, in C or in an intermediate representation (e.g. a DFG) �
� � 33 Some Definitions � • Object Code Object Code: the executable active physical (either HW or SW) implementation of a given functionality � • Core Core: a specific representation of a functionality. It is possible, for example, to have a core described in VHDL, in C or in an intermediate representation (e.g. a DFG) � • IP-Core IP-Core: a core described using a HD Language combined with its communication infrastructure (i.e. the bus interface) �
� 34 Some Definitions � • Object Code Object Code: the executable active physical (either HW or SW) implementation of a given functionality � • Core Core: a specific representation of a functionality. It is possible, for example, to have a core described in VHDL, in C or in an intermediate representation (e.g. a DFG) � • IP-Core IP-Core: a core described using a HD Language combined with its communication infrastructure (i.e. the bus interface) � • Reconfigurable Functional Unit Reconfigurable Functional Unit: an IP-Core that can be plugged and/or unplugged at runtime in an already working architecture �
� � 35 Some Definitions � • Object Code Object Code: the executable active physical (either HW or SW) implementation of a given functionality � • Core Core: a specific representation of a functionality. It is possible, for example, to have a core described in VHDL, in C or in an intermediate representation (e.g. a DFG) � • IP-Core IP-Core: a core described using a HD Language combined with its communication infrastructure (i.e. the bus interface) � • Reconfigurable Functional Unit Reconfigurable Functional Unit: an IP-Core that can be plugged and/or unplugged at runtime in an already working architecture � • Reconfigurable Region Reconfigurable Region: a portion of the device area used to implement a reconfigurable core �
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37 5 W � • who who controls the reconfiguration �
38 5 W � • who who controls the reconfiguration � • where where the reconfiguration cotroller is located �
39 5 W � • who who controls the reconfiguration � • where where the reconfiguration cotroller is located � • when when the configurations are generated �
40 5 W � • who who controls the reconfiguration � • where where the reconfiguration cotroller is located � • when when the configurations are generated � • which which is the granularity of the reconfiguration �
41 5 W � • who who controls the reconfiguration � • where where the reconfiguration cotroller is located � • when when the configurations are generated � • which which is the granularity of the reconfiguration � • in what what dimension the reconfiguration operates �
42 5 W � • who who controls the reconfiguration � • where where the reconfiguration cotroller is located � • when when the configurations are generated � • which which is the granularity of the reconfiguration � • in what what dimension the reconfiguration operates �
43 Physical Coordinates � 4-Slice VIIP CLB
44 Physical Coordinates � SLICE 4-Slice VIIP CLB
45 Physical Coordinates � Y SLICE 4-Slice VIIP CLB X
46 Physical Coordinates � Y SLICE 4-Slice VIIP CLB X 67 66
47 Physical Coordinates � Y SLICE_X67Y75 75 74 4-Slice VIIP CLB X 67 66
48 Physical Coordinates � Y SLICE_X67Y75 SLICE_X66Y74 75 74 4-Slice VIIP CLB X 67 66
49 Physical Coordinates � Y SLICE Switch Box SLICE_X66Y74 75 74 4-Slice VIIP CLB X 67 66
50 Reconfigurable Region Definition � The flows require constraints to be satisfied when defining RRs in the UCF (User Constraints File) file � 50
51 Reconfigurable Region Definition � The flows require constraints to be satisfied when defining RRs in the UCF (User Constraints File) file � AREA_GROUP "RR1" RANGE = SLICE_X28Y64:SLICE_X41Y127; 51
52 Reconfigurable Region Definition � The flows require constraints to be satisfied when defining RRs in the UCF (User Constraints File) file � AREA_GROUP "RR1" RANGE = SLICE_X28Y64:SLICE_X41Y127; AREA_GROUP "RR1" RANGE = RAMB16_X2Y9:RAMB16_X2Y15; 52
53 RR Area Constraints �
54 RR Area Constraints � Xilinx S3 Xilinx VIIP
55 RR Area Constraints � Xilinx S3 Xilinx VIIP
56 RR Area Constraints � Xilinx S3 Xilinx VIIP
57 RR Area Constraints � Xilinx V4 Xilinx S3 Xilinx VIIP
Advanced Topics on Heterogeneous System Architectures Questions… � FPGA Reconfiguration � Politecnico di Milano � Seminari Room, Bld 20 � 4 December, 2017 � Antonio R. Antonio R. Miele Miele � Marco D. Santambrogio Marco D. Santambrogio � Politecnico di Milano �
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