ATMEL FPGA User Group WORKSHOP Astrium F feedback on the ATF280 - PowerPoint PPT Presentation

ATMEL FPGA User Group WORKSHOP Astrium F feedback on the ATF280 part of CNES study “In-flight reconfiguration of FPGA” n°R-S08/TG-0002-034 Florent MERLAY – ASE3

2 Summary  Context This document is the property of Astrium. It shall not be communicated to third parties without prior written agreement. Its content shall not be disclosed.  In-flight reconfigurations of FPGA : use and types  Design rules for reconfigurable units  Reconfigurations using ATF280E  Test design and procedure  Questions Atmel FPGA User Group Workshop - ESTEC 2010/03/03

This document is the property of Astrium. It shall not be communicated to third parties without prior written agreement. Its content shall not be disclosed. 3 Atmel FPGA User Group Workshop - ESTEC 2010/03/03 Context

Context 4  This work is part of the CNES «In-flight reconfiguration of FPGA» R&D study This document is the property of Astrium. It shall not be communicated to third parties without prior written agreement. Its content shall not be disclosed.  The responsible at CNES is Jean BERTRAND  This contract is managed by Astrium F Elancourt with the contribution of Astrium F Toulouse for system maters  This R&D study is divided in 2 parts :  part 1 : Theoretical study  part 2 : Mock-up Atmel FPGA User Group Workshop - ESTEC 2010/03/03

Content of the study 5  The theoretical study (part 1) deals with:  the study of reconfiguration features offered and constraints imposed by reconfigurable FPGAs This document is the property of Astrium. It shall not be communicated to third parties without prior written agreement. Its content shall not be disclosed.  the evaluation of software allowing the reconfiguration of eligible FPGAs and the definition of a partial reconfiguration flow for each one  the definition of design rules for reconfigurable systems meant to be embedded in FPGAs  the study of system/board architectures allowing reconfiguration  the study of impacts on the embedded software of the introduction of reconfigurability  Part 2 aims at designing a demonstrator and providing a test report  This presentation only features part of the theoretical study Part 1 report is available from CNES on demand Atmel FPGA User Group Workshop - ESTEC 2010/03/03

Eligible FPGAs & Trade-off 6  Focus has been put on rad-hard reconfigurable FPGAs 2 eligible components : the SIRF (Xilinx) & the ATF280 (Atmel) Dealing with radiations adds many constraints which interfere with the primary objective This document is the property of Astrium. It shall not be communicated to third parties without prior written agreement. Its content shall not be disclosed.  Reconfiguration capabilities of both FPGAs have equally been studied  Xilinx benefits from its on-ground experience of reconfiguration The SIRF offers an internal reconfiguration interface and dedicated options A PlanAhead add-on can be used to generate partial reconfiguration bitstreams As it is radiation hardened, the FPGA is obviously ITAR  Atmel offers a FPGA with equal reconfiguration capabilities but no dedicated software The FPGA is non-ITAR  ATF280 has been chosen over the SIRF for mock-up in order to address the growing demand of non-ITAR FPGA while proving the reconfiguration capabilities of the ATF280 Atmel FPGA User Group Workshop - ESTEC 2010/03/03

This document is the property of Astrium. It shall not be communicated to third parties without prior written agreement. Its content shall not be disclosed. 7 In-flight reconfigurations of FPGA Atmel FPGA User Group Workshop - ESTEC 2010/03/03 Use & types

Use of in-flight reconfigurations 8  Late design modifications The increasing computational power required by data-processing payloads can no longer be solely addressed by software algorithms. Part of the data-processing is thus performed This document is the property of Astrium. It shall not be communicated to third parties without prior written agreement. Its content shall not be disclosed. using hardware: ASICs. Due to long manufacturing delay, ASICs must be designed early on in projects.  replacing some of them with reconfigurable FPGAs would allow late modifications  Experimental satellites Using reconfigurable FPGAs in experimental satellites payloads would allow operators to adapt data-processing to mission updates as well as enable the use of new algorithms  Telecommunication satellites SatCom satellites being designed for longer and longer missions (up to 18 years for the current generation), it’s getting useful to anticipate the periodical obsolescence of data transmission standards by allowing the update of components in charge of these functionalities Atmel FPGA User Group Workshop - ESTEC 2010/03/03

In-flight reconfiguration types 9  Static reconfiguration Implemented function inhibited during the reconfiguration This document is the property of Astrium. It shall not be communicated to third parties without prior written agreement. Its content shall not be disclosed.  Total : configuration memory either fully overwritten or erased then rewritten  can be used to fix bugs, update algorithms, …  Partial : configuration memory partially overwritten  can be used to swap one of the implemented functions  Dynamic partial reconfiguration Part of the implemented functionality remains active  can be used to swap one of the implemented functions without having to put the whole design on hold Atmel FPGA User Group Workshop - ESTEC 2010/03/03

This document is the property of Astrium. It shall not be communicated to third parties without prior written agreement. Its content shall not be disclosed. 10 Design rules for reconfigurable units Atmel FPGA User Group Workshop - ESTEC 2010/03/03

Disturbance created by reconfiguration 11 The array section holding the dynamic entity  is in an unstable state during reconfigurations: This document is the property of Astrium. It shall not be communicated to third parties without prior written agreement. Its content shall not be disclosed. Values of peripheral signals used as inputs by the rest of the design can change due to routing modification  comes out in an undefined state at the end of reconfigurations: Values of peripheral signals used as outputs by the rest of the design are likely to be used to change flip-flop states Flip-flops aren’t reset by reconfiguration and consequently remain in the state they were in before that operation  ensure that the reconfigured entity comes out of reconfigurations in a predictable state and doesn’t prevent the rest of the design from running normally during the reconfiguration Atmel FPGA User Group Workshop - ESTEC 2010/03/03

Deducted design constraints 12  Predictable state after reconfiguration  Reset This document is the property of Astrium. It shall not be communicated to third parties without prior written agreement. Its content shall not be disclosed.  Static reconfiguration Whole design must be reset  no specific impact  Dynamic reconfiguration Whole design can’t be reset  dedicated reset logic must be added to the static entity and enabled during the reconfiguration Atmel FPGA User Group Workshop - ESTEC 2010/03/03

Deducted design constraints 13  Problem: reconfiguring the dynamic entity can disturb the static entity Directly: uncontrolled dynamic entity outputs can trigger events  i.e.: unwanted AHB bus requests, interrupts, … This document is the property of Astrium. It shall not be communicated to third parties without prior written agreement. Its content shall not be disclosed.  Indirectly: dynamic entity unavailable The static entity requires that the dynamic entity performs operations it cannot perform, being reconfigured i.e.: watchdog put on hold  Suggested solution : replace the dynamic entity during reconfiguration Atmel FPGA User Group Workshop - ESTEC 2010/03/03

Deducted design constraints 14  Example : 1553 Bus controller Triggers all transfers performed on the bus TX/TXB output signals kept in Idle state during reconfiguration This document is the property of Astrium. It shall not be communicated to third parties without prior written agreement. Its content shall not be disclosed.  Well fitted interfaces  Master interfaces (i.e.: AHB master, 1553 bus controller, …) The most adapted to reconfiguration  their outputs shall be kept in an Idle state during reconfiguration  Slave interfaces not used during reconfiguration As adapted as master interfaces  their outputs shall be kept in a state that makes them transparent  Slave interfaces likely to be used during reconfiguration  With delayed/error answer capability: rather complex maintenance module  Without: shouldn’t be reconfigured Atmel FPGA User Group Workshop - ESTEC 2010/03/03

This document is the property of Astrium. It shall not be communicated to third parties without prior written agreement. Its content shall not be disclosed. 15 Reconfiguration using ATF280E Atmel FPGA User Group Workshop - ESTEC 2010/03/03