Dynamically-Controlled Power-Gated FPGAs: Overview and Current - PowerPoint PPT Presentation

Dynamically-Controlled Power-Gated FPGAs: Overview and Current Status 8 th Cascadia FPGA Workshop August 13 th , 2012 Assem Bsoul and Steve Wilton {absoul, stevew}@ece.ubc.ca Funded by Altera Corp. & NSERC System-on-Chip Research Group Department of Electrical and Computer Engineering University of British Columbia Vancouver, B.C., Canada

Power-Gated FPGAs - Vision Application µProcessor IP core 1 IP core 2 IP core 3 IP core 4 IP core 5 CAD Tools Power intent Architecture IP C2 IP C3 IP C1 (Always-on) Power domains - can be powered down when IP C4 Controller idle to reduce static power µProcessor (Power-gated) 2 IP C5

Why do we need a new FPGA? FPGA leakage power is a major component of total power – Almost the same amount as dynamic power for 28nm • Cyclone V: Static 32%, Dynamic 42%, I/O 26%* • Xilinx 7 Series FPGAs: Static 32%, Dynamic 36%, I/O 32%** High-end FPGAs are power hungry – Entering an era where we can’t turn it all on at once! – Large power leads to heat issues � reliability, cooling cost Many applications can benefit from lower power FPGAs – Many applications have regions with long idle periods – E.g., mobile hand-held devices, medical devices, etc. 3 *Altera WP-01158-2.0: Meeting the Low Power Imperative at 28nm **Xilinx WP389 (v1.1): Lowering Power at 28nm with Xilinx 7 Series FPGAs

Challenges FPGAs need to be flexible to support wide range of apps. No prior information about application structure – Modules’ (power domains) sizes and locations are not known 4 Always-on

Challenges – Continued How applications are mapped to devices? CAD challenges Application and power specification Physical synthesis on power-gated chip Architecture challenges: – Dynamically-controlled power gating regions – Enable routing control signals – Wakeup (inrush) current 5

Power-Gated FPGAs Application µProcessor IP core 1 IP core 2 IP core 3 IP core 4 CAD Tools Power intent Architecture Always-on Always-on Controller 6

Power-Gated FPGAs – Applications Application µProcessor IP core 1 IP core 2 IP core 3 IP core 4 CAD Tools Power intent Architecture Always-on Always-on Controller 7

Applications Many suitable applications with long idle periods, e.g.: – Mobile hand-held devices – Head-mounted display system – Medical robot Example: Head-mounted display system – Part of internship at Recon Instruments Inc. – NIOS II processor idle for ≈ 80% of the time Read sensors Sleep and render image 8

Applications – Medical Robot Control Collaboration with Imperial College London – Kuen Hung Tsoi (Brittle) Target: improve safety in minimally-invasive surgery – Control (manually) snake-shaped robot with haptic guidance – Response time ≈ 1ms Proximity Query algorithm: – How close to the cylinder wall? – FPGA design with FP computations 9

Power-Gated FPGAs – CAD Tools Application µProcessor IP core 1 IP core 2 IP core 3 IP core 4 CAD Tools Power intent Architecture Always-on Always-on Controller 10

Power Specification UPF and CPF are commonly used in industry create_power_domain PD_blue -include_scope create_power_domain PD_green -elements { I1 } create_supply_net VDD -domain PD_blue create_supply_net VSS -domain PD_blue … create_power_switch PSW -domain PD_blue create_power_switch PSW -domain PD_blue -output_supply_port { VDD_SW VDD_SW } \ -output_supply_port { VDD_SW VDD_SW } \ -input_supply_port { VDD VDD } -control_port { pon pon } \ -input_supply_port { VDD VDD } -control_port { pon pon } \ -on_state { on VDD pon } \ -on_state { on VDD pon } \ -off_state {off !pon} -off_state {off !pon} Or do we need to create a new standard? – Specify application behaviour, then – Generate power intent and create power controller 11

CAD Flow Application and power intent Partitioning Maximize resources that can be powered down at run-time. Floorplanning Synthesis Placement and 12 Routing

CAD Flow Application and power intent - Constraint placement of power-gated modules in the device. Partitioning - Minimize overlap between always-on and power-gated modules. Floorplanning Always-on Always-on Controller Synthesis Placement and 13 Example floorplan Routing

CAD Flow Application and power intent Partitioning Floorplanning - Group related blocks together (placement). Synthesis - Maximize power-gated routing resources (routing). Placement and 14 Routing

Power-Gated FPGAs – Architecture Application µProcessor IP core 1 IP core 2 IP core 3 IP core 4 CAD Tools Power intent Architecture Always-on Always-on Controller 15 15

Architecture Divide FPGA device into power-controlled regions – Support dynamically-controlled sleep mode Use general-purpose routing fabric for control signals Power control signal Power control signal Power domain Designed on FPGA resources Power gating region Power controller 16

Power Gating Region V DD connection blocks From bordering Architecture granularity 0 - Share sleep transistor among 1 PG_CNTL “region” of tiles. CB CB SB SB SB LC LC CB CB CB Control signal from bordering routing channels. CB CB SB SB SB CB LC CB LC CB Interesting tradeoff: CB CB SB SB SB - Area vs. CAD difficulty Power gating region, size 2x2 17

Power-Gated Switch Blocks Turn off idle SBs – Currently we turn off each SB as a unit – Future work: fracturable SB turn off Always-on SBs are used to: – route power control signals – route signals between different modules in an app. SLEEP Configured to always-on Configured to dynamically-controlled 18

Wakeup (Inrush) Current Inrush current during the wakeup phase – Amount need to be limited to a safe limit – No prior information about which regions to turn on sequentially V DD OFF ON SLEEP Power switch Current (mA) Power-gated Module Voltage on power grid 19 Time

Handling Inrush Current V DD SRAM 0 1 in ∆ T Virtual V DD ∆ T P ∆ T MUX out D ∆ T E ∆ T Power Gating Region SLEEP ∆ T Programmable delay element (PDE) From bordering routing channels PDE size (number of inputs) ≡ the largest power -gated app. that can be turned on using one control signal. 20

Handling Inrush Current – Example 1 C 1 C 1 C 1 C 1 21

Handling Inrush Current – Example 2 C 1 C 2 C 1 C 2 C 1 C 1 22

Power Saving Results Logic clusters and SBs are powered down in a module – Assume worst-case always-on SBs = 32% of SBs in a module – Sweep module size Region size = 2x2 23

Power Saving Results Logic clusters and SBs are powered down in a module – Assume worst-case always-on SBs = 32% of SBs in a module – Sweep module size Region size = 2x2 Region size = 3x3 24

Power Saving Results Logic clusters and SBs are powered down in a module – Assume worst-case always-on SBs = 32% of SBs in a module – Sweep module size Region size = 2x2 Region size = 3x3 Region size = 4x4 For module size 24x24 tiles, region size = 4x4, savings are 70% 25

Current Status Application µProcessor IP core 1 IP core 2 IP core 3 IP core 4 CAD Tools Power intent Architecture Always-on Always-on Controller 26

Current Status Application µProcessor IP core 1 IP core 2 -Implementing robot control -next: evaluation IP core 3 IP core 4 CAD Tools Power intent Architecture Always-on Always-on Controller 27

Current Status Application µProcessor IP core 1 IP core 2 IP core 3 IP core 4 -Packing with constraints -next: high level and low level CAD Tools Power intent Architecture Always-on Always-on Controller 28

Current Status Application µProcessor IP core 1 IP core 2 IP core 3 IP core 4 CAD Tools Power intent -Logic blocks power gating Architecture Always-on Always-on -Handling inrush current -next: switch blocks power gating Controller 29

Contributors Steve Wilton (Supervisor, UBC) Architecture – Assem Bsoul (UBC) Power Model – Jeffrey Goeders (UBC) >>>>>>>>>>>>> CAD – Alshahna Jamal (UBC) Application – Kuen Hung Tsoi (Imperial College London) Power Specification – Kenneth Kent (UNB) 30