The BIST History of FPGAs FPGAs The BIST History of The BISTory BISTory of of FPGAs FPGAs The Chuck Stroud Chuck Stroud Electrical and Computer Engineering Electrical and Computer Engineering Auburn University Auburn University 1
Outline of Presentation Outline of Presentation � Background � Background � Overview of � Overview of FPGAs FPGAs & FPGA Testing & FPGA Testing � My Experience in � My Experience in FPGAs FPGAs � BIST Approaches for � BIST Approaches for FPGAs FPGAs � Logic BIST Approaches � Logic BIST Approaches � CAD Tool Features vs. Testability � CAD Tool Features vs. Testability � Routing BIST Approaches � Routing BIST Approaches � Other Cores & Resources � Other Cores & Resources � Embedded Processor � Embedded Processor- -Based BIST Based BIST � Summary � Summary 2
FPGA Characteristics FPGA Characteristics � Configuration memory � Configuration memory � 32K � 32K - - 50M bits 50M bits � Array of Programmable Logic Blocks ( � Array of Programmable Logic Blocks (PLBs PLBs) ) � 100 � 100 - - 22,270 22,270 PLBs PLBs per FPGA per FPGA � 1 � 1- -8 4 8 4- -input input LUTs LUTs and 1 and 1- -8 flip 8 flip- -flops per PLB flops per PLB � Programmable interconnect network � Programmable interconnect network � Wire segments � Wire segments � 50 � 50 - - 400 per PLB 400 per PLB � Programmable switches � Programmable switches � 80 � 80 - - 2,400 per PLB 2,400 per PLB � Programmable I/O cells � Programmable I/O cells � Bi � Bi- -direction buffer with flip direction buffer with flip- -flops/latches flops/latches � 50 � 50 - - 750 per FPGA 750 per FPGA 3
Important Trends in FPGAs Important Trends in FPGAs � Dynamic partial reconfiguration � Dynamic partial reconfiguration � Incorporating specialized cores � Incorporating specialized cores � RAMs � RAMs - - single single- -port, dual port, dual- -port, FIFO, ECC port, FIFO, ECC � 128 � 128 - - 18K bits per RAM 18K bits per RAM � 4 � 4 - - 550 per FPGA 550 per FPGA � DSPs � DSPs including multipliers, accumulators, etc. including multipliers, accumulators, etc. � 30 � 30 - - 510 per FPGA 510 per FPGA � Embedded processor cores � Embedded processor cores � Up to 2 hard cores per FPGA � Up to 2 hard cores per FPGA � Also support soft processor cores synthesized in FPGA � Also support soft processor cores synthesized in FPGA � Internal access to configuration memory � Internal access to configuration memory � Write and read access by embedded processor core � Write and read access by embedded processor core � FPGAs becoming more like � FPGAs becoming more like SoCs SoCs � ASICs & � ASICs & SoCs SoCs now incorporate FPGA cores now incorporate FPGA cores 4
FPGA Testing Challenges FPGA Testing Challenges � Programmability � Programmability � Must test all modes of operation � Must test all modes of operation � Architectures designed for applications � Architectures designed for applications � Testing issues/problems left to product/test engineers � Testing issues/problems left to product/test engineers � CAD tools designed for high � CAD tools designed for high- -level synthesis level synthesis � Do not support control of proper test conditions � Do not support control of proper test conditions � Constantly growing sizes � Constantly growing sizes � Reconfiguration dominates test time � Reconfiguration dominates test time � Constantly changing architectures � Constantly changing architectures � Architectural features/limitations directly affect � Architectural features/limitations directly affect testability and test development testability and test development � Incorporation of many new/different cores � Incorporation of many new/different cores 5
FPGA Testing FPGA Testing � Typically partitioned for logic and routing � Typically partitioned for logic and routing � But both resources needed to test each other � But both resources needed to test each other � External testing � External testing � Good for manufacture testing only � Good for manufacture testing only � Tests applied via I/O pins � Tests applied via I/O pins � Package dependent and limited by I/O pins � Package dependent and limited by I/O pins � Boundary Scan (only with INTEST) � Boundary Scan (only with INTEST) � Extremely long test time � Extremely long test time � Internal Testing (BIST) � Internal Testing (BIST) � Good for manufacturing & system � Good for manufacturing & system- -level test level test � Good for embedded FPGA cores � Good for embedded FPGA cores 6
FPGA Testing FPGA Testing � Application independent testing � Application independent testing � Test all resources in FPGA � Test all resources in FPGA � Good for manufacturing testing � Good for manufacturing testing many test configurations Requires many � Requires � test configurations � Long test time � Long test time - - downloads dominate test time downloads dominate test time � No area/performance penalty in system � No area/performance penalty in system � Application specific testing � Application specific testing � Test only resources used by system function � Test only resources used by system function � Requires fewer configurations � Requires fewer configurations � But requires new tests for new applications � But requires new tests for new applications � Good for system � Good for system- -level testing only level testing only � Area/performance penalty for test circuitry � Area/performance penalty for test circuitry 7
System- -Level FPGA Testing Level FPGA Testing System � System � System- -level test of FPGA level test of FPGA- -based designs based designs � Diagnostic software for test in system mode � Diagnostic software for test in system mode � Many months of diagnostic code development � Many months of diagnostic code development � Good diagnostic resolution difficult to achieve � Good diagnostic resolution difficult to achieve � DFT/BIST in FPGA (for system � DFT/BIST in FPGA (for system- -level test) level test) � Area penalty typically 10 � Area penalty typically 10- -30% 30% � Performance penalty typically 2 � Performance penalty typically 2- -3 gate delays 3 gate delays � Less logic for system function � Less logic for system function � Longer design time � Longer design time 8
BIST for FPGAs FPGAs BIST for Basic idea: reprogram FPGA to test itself � Basic idea: � reprogram FPGA to test itself � BIST logic disappears after test � BIST logic disappears after test � No area overhead or performance penalties � No area overhead or performance penalties � Applicable to all levels of testing � Applicable to all levels of testing � Application independent testing � Application independent testing � A generic test for a generic component � A generic test for a generic component � Good diagnostic resolution � Good diagnostic resolution � To faulty PLB or wire segment/switch within FPGA � To faulty PLB or wire segment/switch within FPGA � No diagnostic code development or DFT design � No diagnostic code development or DFT design Cost: � Cost: � � Memory to store BIST configurations � Memory to store BIST configurations � Goal: Goal: minimize number of configurations � minimize number of configurations � Download time to execute BIST configurations � Download time to execute BIST configurations � Goal: Goal: minimize downloads � minimize downloads 9
My BIST & FPGA Background My BIST & FPGA Background � Bell Labs (1977 � Bell Labs (1977- -93) 93) � Telecommunications systems � Telecommunications systems � I designed � I designed � 21 production VLSI devices � 21 production VLSI devices � Prototype boards for over half of these � Prototype boards for over half of these � 3 production printed circuit boards � 3 production printed circuit boards � 1981 � 1981 - - began work on BIST began work on BIST � Most VLSI devices included BIST � Most VLSI devices included BIST � 1984 � 1984 - - began work on began work on FPGAs FPGAs � 1985 � 1985 - - began work on synthesis tools began work on synthesis tools � 1987 � 1987 - - first mixed first mixed- -signal BIST signal BIST 10
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