Overview of Virtex Virtex 4 4 Overview of & Virtex Virtex 4 BIST Project 4 BIST Project & 1/18/06 VLSI Design & Test Seminar 1
FPGA Testing Challenges FPGA Testing Challenges � Programmability Programmability � � Must test all modes of operation Must test all modes of operation � � Architectures designed for applications Architectures designed for applications � � Testability is after thought Testability is after thought � � Left to product/test engineers Left to product/test engineers � Constantly growing size � Constantly growing size � � Reconfiguration dominates test time Reconfiguration dominates test time � � Constantly changing architectures Constantly changing architectures � � Incorporation of new and different cores Incorporation of new and different cores � 1/18/06 VLSI Design & Test Seminar 2
Xilinx Virtex Virtex 4 FPGAs 4 FPGAs Xilinx � Array of 1,536 to 22,272 PLBs Array of 1,536 to 22,272 PLBs � =Xtreme DSP =PLBs � 4 4 LUTs/RAMs LUTs/RAMs (4 (4- -input) input) � =Block RAMs/FIFOs =I/O Buffers � 4 4 LUTs LUTs (4 (4- -input) input) � =Guard Band Area � 8 FF/latches 8 FF/latches � � 48 to 552 18K 48 to 552 18K- -bit dual bit dual- -port port � RAMs RAMs PPC Also operate as FIFOs FIFOs � Also operate as � � Also operate as 36K Also operate as 36K- -bit bit RAMs RAMs � with ECC (Hamming) with ECC (Hamming) PPC � 32 to 512 DSP cores 48 32 to 512 DSP cores 48- -bits bits � � 0 to 2 PowerPC processor 0 to 2 PowerPC processor � cores cores 1/18/06 VLSI Design & Test Seminar 3
Virtex 4 BIST Project 4 BIST Project Virtex � BIST for BIST for CLBs CLBs = = Sachin Sachin Dhingra Dhingra � BIST for I/O Buffers = Sudheer Sudheer Vemula Vemula � BIST for I/O Buffers = � � BIST for BIST for RAMs RAMs & & DSPs DSPs = Daniel Milton = Daniel Milton � � Guard Band (w/BIST) = Lee Lerner Guard Band (w/BIST) = Lee Lerner � BIST for Interconnect = Chuck Stroud � BIST for Interconnect = Chuck Stroud � � Project scheduled for completion this Project scheduled for completion this � year year 1/18/06 VLSI Design & Test Seminar 4
Logic BIST for Virtex 4 Logic BIST for Virtex 4 FPGAs Using Embedded FPGAs Using Embedded Microprocessor Microprocessor VLSI Design & Test Seminar - January 2006 Sachin Sachin Dhingra Dhingra 1/18/06 VLSI Design & Test Seminar 5
Outline Outline � Introduction Introduction � � Partial Configuration Readback Partial Configuration Readback � � Comparison Comparison � � Virtex 2 Pro Virtex 2 Pro � � Virtex 4 Virtex 4 � � Logic BIST Using Embedded Processor Logic BIST Using Embedded Processor � � PowerPC/Microblaze PowerPC/Microblaze � � New approach New approach � � Circular Comparison BIST Architecture Circular Comparison BIST Architecture � 1/18/06 VLSI Design & Test Seminar 6
Introduction Introduction � Built Built- -In Self Test (BIST) for FPGAs In Self Test (BIST) for FPGAs � � Program some Programmable Logic Blocks (PLBs) as Test Pattern � Program some Programmable Logic Blocks (PLBs) as Test Pattern Generators (TPGs) and Output Response Analyzers (ORAs) to test Generators (TPGs) and Output Response Analyzers (ORAs) to test the remaining resources of the FPGA the remaining resources of the FPGA � Diagnosis and Fault Tolerant Operation Diagnosis and Fault Tolerant Operation � � No area overhead � No area overhead � Issues Issues � � Large number of Configurations => High memory requirements Large number of Configurations => High memory requirements � � Slow Configuration Speeds => Long test times Slow Configuration Speeds => Long test times � Proposed Solutions � Proposed Solutions � � Partial Reconfiguration Partial Reconfiguration � � Partial Configuration Memory Readback Partial Configuration Memory Readback � � BIST using Embedded Processor BIST using Embedded Processor � 1/18/06 VLSI Design & Test Seminar 7
Partial Configuration Memory Readback Partial Configuration Memory Readback � Recent FPGAs allow configuration Recent FPGAs allow configuration � memory readback of only a section memory readback of only a section of FPGA of FPGA � Column based configuration Column based configuration � memory using frames spanning memory using frames spanning entire columns entire columns � Only the frames containing BIST Only the frames containing BIST � results are read results are read � Frames for FFs in ORA columns only Frames for FFs in ORA columns only � Empty PLB Empty PLB � Time saved compared to Full Time saved compared to Full � Block Under Test (BUT) Block Under Test (BUT) Configuration Memory Readback Configuration Memory Readback Output Response Analyzer (ORA) Output Response Analyzer (ORA) � Saves Logic & Routing resources Saves Logic & Routing resources � Test Pattern Generator (TPG) Test Pattern Generator (TPG) ORA Flip- -Flip Flip � Scan Chain is absent Scan Chain is absent ORA Flip � 1/18/06 VLSI Design & Test Seminar 8
Comparison of V2P and V4 Comparison of V2P and V4 for Logic BIST for Logic BIST Virtex 2 Pro Virtex 4 Virtex 2 Pro Virtex 4 Virtex 2 Pro Virtex 4 PLB All four Identical slices 2 slices of 2 types PLB All four Identical slices 2 slices of 2 types SliceL (logic) & SliceM (memory) SliceL (logic) & SliceM (memory) XDL XDL Row- Row -Column CLB co Column CLB co- -ordinates ordinates XY CLB co- XY CLB co -ordinates ordinates Minor changes from Virtex I Minor changes from Virtex I Similar to V2P w/ minor changes Similar to V2P w/ minor changes Location of 2 PPCs PPCs Left and Right Halves Top and Bottom Halves Location of 2 Left and Right Halves Top and Bottom Halves Slice Testability Slice Testability Poor Poor Better Better 1/18/06 VLSI Design & Test Seminar 9
BIST Using Embedded Processor BIST Using Embedded Processor � Embedded Processor runs BIST and diagnosis Embedded Processor runs BIST and diagnosis � � PowerPC � PowerPC � Microblaze Microblaze � � No dedicated resources for embedded processor No dedicated resources for embedded processor � � FPGA resources are required for interface to FPGA resources are required for interface to � � Program memory (block Program memory (block RAMs RAMs) ) � � Internal Configuration Access Port (ICAP) Internal Configuration Access Port (ICAP) � � UART (hyper UART (hyper- -terminal interface to PC) terminal interface to PC) � Read- -Modify Modify- -Write using ICAP module Write using ICAP module � Read � � Fast partial reconfiguration Fast partial reconfiguration � � Verification and debug procedure for development Verification and debug procedure for development � � Fault injection emulation � Fault injection emulation � FPGA is divided in two sections for testing: FPGA is divided in two sections for testing: � � Embedded Processor Embedded Processor � � BIST circuitry BIST circuitry � 1/18/06 VLSI Design & Test Seminar 10
Embedded Processors in V2P Embedded Processors in V2P Microblaze - Soft Core PowerPC - Hard Core ( Can be placed anywhere on the device ) ( Fixed position in a device ) 1/18/06 VLSI Design & Test Seminar 11
Comparing Embedded Processors Comparing Embedded Processors Microblaze PowerPC Microblaze PowerPC Location Variable – Fixed - Location Variable Fixed – can be can be - hard core has fixed hard core has fixed located anywhere in FPGA located anywhere in FPGA location in FPGA location in FPGA Availability all Virtex 2, Virtex 2 Selected Virtex 2 Pro Availability all Virtex 2, Virtex 2 Selected Virtex 2 Pro Pro, Virtex Virtex 4 devices 4 devices and Virtex 4 FX only Pro, and Virtex 4 FX only Speed 200 MHz (max) 450 MHz (max) Speed 200 MHz (max) 450 MHz (max) Compiler* EDK EDK Compiler* EDK EDK Slice count 1000 1035 Slice count 1000 1035 Slice count** 900 820 Slice count** 900 820 BRAM count 40 36 BRAM count 40 36 BRAM count** 16 16 BRAM count** 16 16 * Processor type is EDK compiler option - same code works for both Microblaze and PowerPC without any modifications ** Compacted Design 1/18/06 VLSI Design & Test Seminar 12
BIST Architecture BIST Architecture � BIST in part of the FPGA BIST in part of the FPGA � CUT CUT Embedded Processor occupies rest � Embedded Processor occupies rest � Embedded Embedded � Hard core or Hard core or � Processor Processor � Soft core (easier to move) Soft core (easier to move) � Small Devices � Embedded processor also consists Embedded processor also consists � of peripheral devices: of peripheral devices: � UART UART � Embedded � Memory interface � Memory interface Embedded CUT CUT Processor Processor � BUS arbiter BUS arbiter � � ICAP Module ICAP Module � � BIST and processor swap places BIST and processor swap places � Large Devices for next test session for next test session 1/18/06 VLSI Design & Test Seminar 13
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