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Reconfigurable Computing Computing Reconfigurable Partial reconfiguration reconfiguration design design Partial Chapter 8 8 Chapter Prof. Dr.- -Ing. Jürgen Teich Ing. Jürgen Teich Prof. Dr. Lehrstuhl für Hardware- -Software Software- -Co Co- -Design Design Lehrstuhl für Hardware Reconfigurable Computing

Partial Reconfiguration Design - - Introduction Introduction Partial Reconfiguration Design � Reconfiguration advantages � Fast computation compared to GPP � Flexible computation compared to ASIC video mp3 Out � Partial device re-use allows Video � in Space saving PS2 MPEG2 � control Power saving VHDL Video out MPEG MPEG Control MP3 MP3 Time Reconfigurable Computing 2

Partial Reconfiguration Design - - Introduction Introduction Partial Reconfiguration Design � A partially reconfigurable design consists of: � A set of full reconfigurable designs � A set of partial designs which can be separately downloaded � The full designs as well as the partial modules are available as full (partial) bitstream used to configure the device � The partially reconfigurable modules are use to move the system from one configuration to the next one Reconfigurable Computing 3

Partial reconfiguration design - - Introduction Introduction Partial reconfiguration design � The purpose of this section is to learn how to design a partially reconfigurable system using the current CAD tools and devices � The Xilinx FPGAs (Virtex-II and Spartan-II) are some of the few devices on the market allowing partial reconfiguration � This section will focus on two Xilinx-based methodologies for designing a partially reconfigurable system: � The Xilinx partial design flow � The Xilinx small bit modifcation using JBits Reconfigurable Computing 4

Partial reconfiguration design - - Approach Approach Partial reconfiguration design � Traditional design flow Basic Constraints + VHDL (pins, timing, …) � Full circuit � Constraints define: � Placement Constraints All constraints provided earlier � Relative Location Constraints Netlist � Timing Constraints � Only one full circuit is generated Technology Mapping Place and route Full Bitstream Reconfigurable Computing 5

Partial reconfiguration design - - Approach Approach Partial reconfiguration design � Partial reconfiguration flow: Basic Constraints (pins, timing, …) � Placement constraints + VHDL Placement Constraints must be provided (block positions and area) � Modules are compiled separately � The result is a set of full and Netlist 1 Netlist 2 Netlist 3 Netlist 1 Netlist 2 Netlist 3 partial implementations (EDIF and bitstream). Full Partial � The partial reconfigurable bitstreams are used to move Technology Mapping Place and route the device from one configuration to another. Full Full Full partial partial partial Bitstream 1 Bitstream 2 Bitstream 3 Bitstream 1 Bitstream 2 Bitstream 3 Reconfigurable Computing 6

Partial reconfiguration design - - Approach Approach Partial reconfiguration design � Delaying placement constraints increases degree of freedom VHDL SystemC HandelC Basic Basic Basic constraints constraints constraints Area constraints provided after a first evaluation Placement Constraints + Netlist 1 Netlist 2 Netlist 3 Netlist 1 Netlist 2 Netlist 3 (block positions and area) Full Partial Technology Mapping Run-time Place and route Relocation Full Full Full Placement partial partial partial Bitstream Bitstream Bitstream Bitstream Bitstream Bitstream constraints 1 2 3 1 2 3 Reconfigurable Computing 7

Partial reconfiguration on Xilinx Virtex FPGAs Partial reconfiguration on Xilinx Virtex FPGAs � Create a bitstream database for full and partial modules to be used at run-time for device reconfiguration Reconfigurable Computing 8

The partial design flow The partial design flow � Modular implementation of a large project � The team manager defines the structure of the overall project (top-level) Interfaces � Each designer or team of designers imple- ment and test each module separately � Top1 The implemented modules are inte- grated in the final design mod mod � 3 A top-level consists of 1 � A set of independent modules mod � Interfaces between the modules 2 � Interfaces with the pins � Each module is assigned a given position and area on the device by means of area constraints Reconfigurable Computing 9

The partial design flow The partial design flow � For partial reconfiguration, the goal is to generate � A set of full designs Top3 � A set of partial designs Top2 Top1 � The partial designs are used to move mod mod mod 3 from one full design to another mod 1 mod 3 mod 1 � The input is structured as follows: 3 1 mod � Top_level mod 2 � Module_1 mod 2 � Module_2 2 � … � Module_N � The input language can be any HDL Reconfigurable Computing 10

The partial design flow – – Example Example The partial design flow � Modular design � Static module is fixed for all times Static Partial � Only partial Module Module module can be reconfigured � Insertion of t1 t2 communication Static Partial macros at fixed Module Module t4 t3 positions x y Reconfigurable Computing 11

The partial design flow – – Example VHDL Example VHDL The partial design flow entity TOP is port ( x: in std_logic; y: out std_logic); end TOP; architecture ARCH of Top is component MACRO port ( in1, in2 : in std_logic; out1, out2 : out_std_logic); end component; component STATIC_MODULE port ( x_in, d_in: in std_logic; d_out: out std_logic); end component; component PARTIAL_MODULE port ( d_in: in std_logic; y_out, d_out: out std_logic); end component; signal t1, t2, t3, t4 : std_logic; Reconfigurable Computing 12

The partial design flow – – Example VHDL Example VHDL The partial design flow begin static: STATIC_MODULE port map(x_in=>x, d_in=>t4, d_out=>t1); macro_right2left: MACRO port map (in1=>t1, in2=>open, out1=>t2, out=>open); macro_left2right: MACRO port map (in1=>t3, in2=>open, out1=>t4, out=>open); partial: PARTIAL_MODULE port map(y_out=>y, d_in=>t2, d_out=>t3); end ARCH; � Macro component ís provided by Xilinx and must be inserted in the TOP level for the communication with partial modules � Static and partial modules do not require any additional changes Reconfigurable Computing 13

The partial design flow – – Four Steps Four Steps The partial design flow � 1) Build the top level context � Slice Macros at fixed positions are used to communicate between static design logic and reconfigurable logic. � Note that there is NO logic except IOs and clocks in the top level design. All logic is contained in one or more 'modules' (E.G. AREA_GROUP). � Required files : top.ngc and top.ucf (for constraints) � Output file: top.ngo. � 2) Build the static modules � These are the modules (E.G. logic and routing) that will NOT be dynamically reconfigured. � Required files : .ngc for each static 'module'. � Output files: top_routed.ncd (without reconfigurable logic) Reconfigurable Computing 14

The partial design flow – – Four Steps Four Steps The partial design flow � 3) Build the dynamic modules � Build each flavor of each dynanically reconfigurable module. � Required files : .ngc for each dynamic 'module'. � Output files: Routed .ncd file for each flavor of a dynamically reconfigurable module WITHOUT logic and routing from static modules. Reconfigurable Computing 15

The partial design flow – – Four Steps Four Steps The partial design flow � 4) Assemble full design with each flavor of each dynamically reconfigurable module. Generate the required bitstreams. � Required files : .ncd for static modules and for each flavor of each reconfigurable � Output files: � a bitstream for full design with each flavor of each reconfigurable module � a partial bitstream for each flavor of each reconfigurable module � report file Reconfigurable Computing 16

The partial design flow – – directory structure directory structure The partial design flow � Synth Containts the VHDL code and synthesised Netlists � top � static � Mod1 � … � ModN � Top/Initial Built top level context � Static Built static modules � ReconfigModules Built reconfigurable modules � Merges Contains assembled bitstreams Reconfigurable Computing 17

The partial design flow – – Top level context Top level context The partial design flow � Instantiate static and reconfigurable modules as “black-boxes” � Connect the modules at the top-level using slice macros between reconfigurable and fixed modules � Estimate a rectangular bounding region for each module and constrain it to this area � Constrain top-level I/O ports and slice macros to a fixed locations � The following command must be run in each initial directory under the corresponding Top-level � cd Top/Initial/ � ngdbuild -modular initial top.ngc Reconfigurable Computing 18