Reconfigurable Computing Reconfigurable Computing VHDL Crash Course VHDL Crash Course Chapter 2 Chapter 2 Prof. Dr.- -Ing. J Ing. Jü ürgen Teich rgen Teich Prof. Dr. Lehrstuhl fü ür Hardware r Hardware- -Software Software- -Co Co- -Design Design Lehrstuhl f Reconfigurable Computing
VHDL VHDL VHDL: V ery high speed integrated circuits H ardware D escription L anguage • Hardware description for – patent application – simulation – synthesis of ICs • Description covers the aspects of – wiring – behaviour � structure – hierarchy • Here: only synthesizable subset ! Reconfigurable Computing 2
Entity – – Wrapper and interface definition Wrapper and interface definition Entity • Logical container of an entity ENTITY x • Port definition of the interface: signals x � X x • Signals are defined by an identifier , a direction and a data type Parameter – direction: in , out , inout, buffer – data types: bit, std_logic(_vector), ADT ENTITY ENTITY x1 x1 External signals y y correspong to internal x2 x2 signals. External view Internal view Reconfigurable Computing 3
Entity as a „ „Black Box Black Box“ “ Entity as a • Entity as a „black box“ � seperation of internal structur and behaviour (functionality) • Example: Entity with 2 input and 1 output • Ports are defined but functionallity yet undefined. two_gate Name Port x1 Structure y Port and behaviour? x2 Reconfigurable Computing 4
Entity – – Example Example Entity Used libraries Which packages of Keywords in the library are to blue be used LIBRARY ieee; Header USE ieee.std_logic_1164.all; Name of the Entity definition Entity 2 input signal named x1 ENTITY two_gate IS and x2 PORT ( x1, x2 : IN std_logic; Interface y : OUT std_logic ); END two_gate; output signal data types of the Name of the Entity named y signals (multivalued logic) Reconfigurable Computing 5 Keywords are spelled either in upper or lower case but never mixed!
Architecture – – Behaviour of an Entity Behaviour of an Entity Architecture Architecture x1 • The functionallity of an entity is Structure y described in its architecture. and x2 • The architektur behaviour – has a unique name, – may contain a declaration part for internal signals, – is assigned to an entity. • It is possible to define different architectures for the same Entity. ARCHITECTURE <architecturename> OF <entityname> IS [declaration part] BEGIN [architecture statements] END <architecturename>; Reconfigurable Computing 6
Architecture – – Example Example Architecture Architecture • Example of a NAND gate x1 y & based on the previous x2 entity declaration: Assignment Architecture name Entity Name operator for signals ARCHITECTURE two_gate_nand OF two_gate IS BEGIN y <= NOT ( x1 AND x2 ); Behavioural description: END two_gate_nand; One statement using the predefined Architecture operations: AND, OR, name NOT Reconfigurable Computing 7
Configuration – – the link the link Configuration The configuration assigns a behaviourial description to it's entity. – Different behaviourial descriptions for simulation and synthesis. � different aspects of the functionality � simulation complexity and performance – Interface definition is valid for a class of entities, e.g.: AND, OR, XOR-gates with 2 inputs each � only a new behavioural desciption needs to be created Reconfigurable Computing 8
Configuration – – Example Example Configuration • The configuration assigns an architecture to the entity. two_gate_nand_conf x1 x1 y y & x2 VHDL comments x2 started by: -- Entity name -- Configuration for nand with two Inputs CONFIGURATION two_gate_nand_conf OF two_gate IS FOR two_gate_nand Configuration . . . name END FOR; Name of the architecture to END two_gate_nand_conf; use Reconfigurable Computing 9
Progress Progress • Covered so far: – Entity wrapper and interface definition of the logical unit – Architecture describes the behaviour or structure of the entity – Configuration links one architecture to an entity • Still missing: – Components • to create structural descriptions • to introduce hierarchy – Processes – Control flow, state machines and bit vectors – timing models – simulation using testbenches Reconfigurable Computing 10
Use of components Use of components x1 • Hierarchical use of components & y • Complex gates - example: XOR ≥ – structural description x2 & – ports: 2 inputs and 1 output – reuse of two_gate, with the new name xor_gate. xor Possible structure of the ent1 ent3 entity xor_gate : x1 x1 y x1 & x2 connect1 ¬ Components inv1 y y ≥ ent2 • ent1, ent2 (and gates) x1 y ¬ x2 inv2 & • ent3 (or gates) connect2 x2 x2 • inv1, inv2 (inverter) Reconfigurable Computing 11
XOR- -Entity Entity XOR • Entity declaration LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY xor_gate IS PORT( x1, x2 : IN std_logic; y : OUT std_logic ); END xor_gate; Reconfigurable Computing 12
XOR – – Declarations Declarations XOR • Architecture declaration • Instantiation of components Declaration of a gate with 2 inputs ARCHITECTURE xor_structure OF xor_gate IS and 1 output COMPONENT two_gate PORT ( x1, x2: in std_logic; y: out std_logic ); END COMPONENT; SIGNAL connect1, connect2: std_logic; SIGNAL inv1, inv2: std_logic; BEGIN 2 signals to connect the 2 signals for the and and ... inverted input signals or gates Reconfigurable Computing 13
XOR – – Instantiation Instantiation XOR • Instantiation and connection of the components Connection: i ntern => extern type of entity (from the point of view of the ... component) ent1: two_gate PORT MAP (x1 => x1, x2 => inv1, y => connect1 ); ent2: two_gate PORT MAP (x1 => inv2, x2 => x2, y => connect2 ); ent3: two_gate PORT MAP (x1 => connect1, x2 => connect2, y => y ); ... xor ent1 ent3 instanc x1 x1 y e name x1 & x2 connect1 ¬ inv1 y y ≥ ent2 x1 y ¬ x2 inv2 & x2 connect2 x2 Reconfigurable Computing 14
XOR – – Connections in detail Connections in detail XOR ent1 ent1: two_gate x1 x1 PORT MAP ( x1 => x1, y & x2 => inv1, x2 connect1 y => connect1 ); inv1 ent2 ent2: two_gate x1 y PORT MAP ( x1 => inv2, inv2 x2 & x2 => x2, x2 connect2 y => connect2 ); ent3 x1 ent3: two_gate connect1 PORT MAP ( x1 => connect1, y y ≥ x2 => connect2, y => y ); x2 connect2 Reconfigurable Computing 15
Process evaluation cycle Process evaluation cycle • Evaluation of a process: triggered event – Instruction inside a process are evaluated process sequentially! evaluate sequentially – A process can be considered to be an infinite loop Evaluate signal Variables are assigned and assignments – A process requires at evaluated and forward to least one time immediatly end of process consuming statement (change of signal, time, event) to prevent cycles triggered with no time signals stable requirements Reconfigurable Computing 16
Syntax of a process Syntax of a process Sensitiviy list: Signal changes evoke process Inside an architecture avaluation. Analogous to: „wait for changes ... Process name of x1 or x2“ (optional) BEGIN (alternative: process intern [label:] PROCESS ( x1, x2, ... ) wait-statements) BEGIN Attention: Signal assignments Prozessrumpf; (<=) differ from signal assignment in programming languages! END PROCESS [label]; VHDL JAVA END; Process = A <= B; A = B; name C <= A; C = A; (optional) Reconfigurable Computing 17
Syntax of a process Syntax of a process Signal a, b : bit; ... PROCESS ( a ) Signal Signal Variable Variable v : bit; a b v BEGIN start of process a ini b ini v ini a <= NOT b; _ Sequential evaluation. a ini immediatly v := NOT a; Called until all triggered signals become stable at the b <= a OR v; end of the process . a <= b; _ _ ≡ WAIT ON a ; _ a ini end of process b ini b ini END PROCESS; a ini or a ini Overwrites value! Reconfigurable Computing 18
XOR- -Architecture Architecture XOR • Negation of input signals Process name ... Sensitivity list INV : PROCESS ( x1, x2 ) BEGIN inv1 <= NOT x2; Assignment of negated input signal inv2 <= NOT x1; END PROCESS INV; xor END xor_arch; x1 ¬ inv1 ¬ inv2 x2 Reconfigurable Computing 19
XOR- -Configuration Configuration XOR • Assignment of behavioural descritption to the instantiated entity Entity 1 und 2 CONFIGURATION xor_conf OF xor_gate IS are of type: FOR xor_behavior two_gate FOR ent1,ent2 : two_gate USE ENTITY work.two_gate(two_gate_and); END FOR; Assigned architecture of the entities: AND- FOR ent3 : two_gate gate USE ENTITY work.two_gate(two_gate_or); END FOR; END FOR; Assigned architecture END xor_conf; Entity name of the entity: OR-gate Use the following entity Reconfigurable Computing 20
Recommend
More recommend
