Hardware Design with VHDL VHDL I ECE 443 VHDL Introduction A - PowerPoint PPT Presentation

Hardware Design with VHDL VHDL I ECE 443 VHDL Introduction A language for describing the structural, physical and behavioral characteristics of digital systems. VHDL is used to attain several goals: • Synthesis of digital systems. • Verification and validation of digital systems. • Test vector generation for testing circuits. VHDL supports both structural and behavioral descriptions of a system at multiple levels of abstraction. Structure and behavior are complementary ways of describing systems. A description of the behavior of a system says nothing about its structure. Two components to the description: The interface to the design: entity declaration. The internal behavior of the design: architecture construct. ECE UNM 1 (9/4/08)

Hardware Design with VHDL VHDL I ECE 443 VHDL Basics Basic structure of a VHDL program: library ieee; use ieee.std_logic_1164. all; entity eq1 is port ( i0, i1: in std_logic; eq: out std_logic); end eq1; architecture sop_arch of eq1 is signal p0, p1: std_logic; begin -- sum of two product terms eq <= p0 or p1; -- product terms p0 <= ( not i0) and ( not i1); p1 <= i0 and i1; end sop_arch; ECE UNM 2 (9/4/08)

Hardware Design with VHDL VHDL I ECE 443 VHDL Basics VHDL is case insensitive. Comments start with ’--’ VHDL keywords with be given in bold . The first two lines include the std_logic_1164 package from the ieee library: library ieee; use ieee.std_logic_1164. all; This allows the use of the std_logic data type. The entity declaration defines the I/O signals of the circuit. The mode can be in , out , or inout VHDL is strongly typed language. The data type std_logic has nine possible values. ’0’, ’1’ and ’Z’ can be synthesized. ’U’ and ’X’ (uninitialized and unknown) occur in simulation ’-’, ’H’, ’L’ and ’W’ are not important for this course. ECE UNM 3 (9/4/08)

Hardware Design with VHDL VHDL I ECE 443 VHDL Basics Arrays of wires are defined using std_logic_vector . -- defines an 8-bit input port. a: in std_logic_vector(7 downto 0); Other examples include a(7 downto 4); -- refers to a range; a(1); -- refers to an individual element a: in std_logic_vector(7 to 0); -- ascending order Logical operators including not , and , or and xor are defined for the data types std_logic and std_logic_vector . These operations are applied bitwise for std_logic_vector . The architecture code describes the circuit’s operation. architecture sop_arch of eq1 is signal p0, p1: std_logic; begin ... ECE UNM 4 (9/4/08)

Hardware Design with VHDL VHDL I ECE 443 VHDL Basics VHDL allows multiple bodies to be associated with an entity. The name parameter, sop_arch (for sum of products), is used to distinguish between them. An optional declaration section, e.g., signal , enables local signals to be declared. The statements between the begin ... end are concurrent statements . begin -- sum of two product terms eq <= p0 or p1; -- product terms p0 <= ( not i0) and ( not i1); p1 <= i0 and i1; end sop_arch; They are NOT executed sequentially (as in a C program), they execute in parallel. Remember we are really describing a circuit and its connectivity -- think of this block as a text description of a schematic. ECE UNM 5 (9/4/08)

Hardware Design with VHDL VHDL I ECE 443 VHDL Basics i0 p0 eq i1 p1 Schematic During a simulation of this circuit, the input signals p0 and p1 in the statement eq <= p0 or p1; are monitored for changes. If either signal changes value, the statement is executed and the output signal, eq , is assigned a new value (potentially). Of course, a hardware realization of this schematic behaves in the same manner, albeit, with signal delays. This is a very important concept that distinguishes HDL from programming lan- guages such as C. ECE UNM 6 (9/4/08)

Hardware Design with VHDL VHDL I ECE 443 Structural VHDL The style of VHDL given above is referred to as structural code (as opposed to behavioral code that we’ll get to later). It is characterized by the use of logic gates, such as and and or , and concurrent assignment statements. A circuit can be completely described in a structural representation. The drawback is that larger circuits becomes very complex very quickly, which increases the likelihood that you’ll introduce an error. As with programming languages, one solution to dealing with complexity is through ’divide and conquer’. Here, you break up the code into modules with well-defined interfaces. VHDL allows for modularization using a component instantiation construct. From the previous example, assume we want to create a 2-bit comparator. One way of doing this is to re-use the 1-bit comparators as shown below. ECE UNM 7 (9/4/08)

Hardware Design with VHDL VHDL I ECE 443 Structural VHDL a(0) i0 e0 b(0) eq i1 a_eq_b a(1) i0 eq b(1) e1 i1 architecture struc_arch of eq2 is signal e0, e1: std_logic; begin -- instantiate two 1-bit comparators eq_bit0_unit: entity work.eq1(sop_arch) port map (i0=>a(0), i1=>b(0), eq=>e0); eq_bit1_unit: entity work.eq1(sop_arch) port map (i0=>a(1), i1=>b(1), eq=>e1); -- a and b are equal if both sets of bit are equal a_eq_b <= e0 and e1; end struc_arch; ECE UNM 8 (9/4/08)

Hardware Design with VHDL VHDL I ECE 443 Structural VHDL Component instantiations are given as: unit_label: entity lib_name.entity_name(arch_name) port map (formal1=>actual1, formal2=>actual2, ...); The unit_label labels the instance while lib_name indicates which library contains the component. The work library is the default library where your components are stored. entity_name and arch_name are the names assigned to the component given earlier. ( arch_name is optional -- if omitted, the last compiled arch. body is used). The port map establishes the relationship between the formal signals used in the component definition and the actual signals defined in the caller (parent). Note that the component instantiation stmt is also a concurrent statement. Both instantiated components execute simultaneously, just as they would in hardware. ECE UNM 9 (9/4/08)

Hardware Design with VHDL VHDL I ECE 443 Test Bench A test bench emulates a physical lab bench with test and measurement equipment. It is used for simulation ONLY and therefore will contain statements that may NOT be synthesizable to a hardware implementation. Obviously, you do NOT synthesize the test bench. library ieee; use ieee.std_logic_1164. all ; entity eq2_testbench is -- no ports for test benches! end eq2_testbench; architecture tb_arch of eq2_testbench is signal t_in0, t_in1: std_logic_vector(1 downto 0); signal t_out: std_logic; begin -- instantiate the circuit under test uut: entity work.eq2(struc_arch) port map (a=>t_in0, b=>t_in1, a_eq_b=> t_out); ECE UNM 10 (9/4/08)

Hardware Design with VHDL VHDL I ECE 443 Test Bench process begin -- test vector 1 t_in0 <= "00"; t_in1 <= "00"; wait for 200 ns; -- test vector 2 t_in0 <= "01"; t_in1 <= "00"; wait for 200 ns; ... -- other combinations end process ; end tb_arch; The process statement forces sequential execution -- we’ll get to processes soon. In general, anything that has a ’time’ associated with it, e.g., 200 ns , is not syn- thesizable -- you can’t force hardware delays, but you can model them in sims. ECE UNM 11 (9/4/08)