CDA 4253/CIS 6930 FPGA System Design Finite State Machines Dr. Hao - PowerPoint PPT Presentation

Communication Protocol – Slave When ready to accept data input S0/ready=0 S1/Ready=1 Valid = 1 Valid Ready 39

Case Study 2 Fibonacci Number (section 6.3.1, Chu’s book) 40

Fibonacci Number  if i = 0 0  if i = 1 1 fib ( i ) = fib ( i − 1) + fib ( i − 2)  ex. 0 , 1 , 1 , 2 , 3 , 5 , 8 , 13 , . . . 41

Fibonacci Number – cont’d done/ idle/ start: start the operation done <= ‘1’ done <= ‘0’ f <= t1 done : result is available n : number of iterations n=0 f : output start=‘1’ t0 : register holding fib(i-2) t1 : register holding fib(i-1) op/ t1 <= t1+t0 t0 <= t1 n <= n-1 n/=1 42

Case Study 3 Binary Division (Section 6.3.2, Chu’s Book) 43

144 Binary Division FSMD divisor 0 0 - 0 11 quotient 1 0 0 0 1 0 10 1 - 0 0 0 1 dividend 0000 0001 0000 0011 44 Figure 6.10 Long division of two 4-bit unsigned integers. rh rI Figure 6.11 Sketch of division circuit’s data path. be summarized as follows: 1. Double the dividend width by appending 0’s in front and align the divisor to the leftmost bit of the extended dividend. 2. If the corresponding dividend bits are greater than or equal to the divisor, subtract the divisor from the dividend bits and make the corresponding quotient bit 1. Otherwise, keep the original dividend bits and make the quotient bit 0. 3. Append one additional dividend bit to the previous result and shift the divisor to the right one position. 4. Repeat steps 2 and 3 until all dividend bits are used. The sketch of the data path is shown in Figure 6.11. Initially, the divisor is stored in the d register and the extended dividend is stored in the rh and rl registers. In each iteration, the rh and rl registers are shifted to the left one position. This corresponds to shifting the divisor to the right of the previous algorithm. We can then compare rh and d and perform subtraction if r h is greater than or equal to d. When r h and rl are shifted to the left, the rightmost bit of rl becomes available. It can be used to store the current quotient bit. After

Binary Division Algorithm 1. Double the dividend width by appending ‘0’ to its left. 2. Align the divisor – double its width by appending ‘0’ to its right. 3. If dividend >= divisor, subtract divisor from dividend, and left shift ‘1’ into quotient. Otherwise, left shift ‘0’ into quotient. 4. Right shift divisor one position. 5. Repeat 3 and 4 until the remaining dividend is less than divisor. 45

Binary Division Algorithm 1101 / 0010 = ? Dividend Divisor Quotient 00001101 00100000 align divisor 00001101 00010000 0 right shift divisor 00001101 00001000 00 right shift divisor 00000101 00000100 001 dividend – divisor right shift divisor 00000001 00000010 0011 dividend – divisor right shift divisor 00000001 00000010 00110 dividend < divisor terminate 46

Binary Division Algorithm – FSM 47

Case Study 4 Debouncing Circuit

11 9 Original & Debounced Inputs DESIGN EXAMPLES bounces bounces (last less than 20 ms) (last less than 20 ms) - - original -- switch output - I L debounced output 20 ms- (scheme 1) *Oms , 20ms I debounced output (scheme 2) - ; 20 ms Figure 5.8 Original and debounced waveforms. Figure 5.9 State diagram of a debouncing circuit.

11 9 DESIGN EXAMPLES bounces bounces (last less than 20 ms) (last less than 20 ms) - - original -- switch output - I L debounced output 20 ms- (scheme 1) *Oms , 20ms I debounced output (scheme 2) - ; 20 ms Debouncing Circuit – Scheme 1 Figure 5.8 Original and debounced waveforms. sw : input from slide switches or push buttons. m_tick : input from a timer with 10ms period. See listing 5.6 for VHDL code that implements this FSM 50 Figure 5.9 State diagram of a debouncing circuit.

11 9 DESIGN EXAMPLES bounces bounces (last less than 20 ms) (last less than 20 ms) - - original -- switch output - I L debounced output 20 ms- (scheme 1) *Oms , 20ms I debounced output (scheme 2) - ; 20 ms Figure 5.8 Original and debounced waveforms. Debouncing Circuit – Scheme 1 sw : input from slide switches or push buttons. m_tick : input from a timer with 10ms period. See listing 5.6 for VHDL code that implements this FSM sw.m_tick Figure 5.9 State diagram of a debouncing circuit.

Debouncing Testing Circuit 122 FSM q - - - tick - btn(1) level en edge counter > > hex0 sseg sseg detector - 4 - an - hex1 an db - tick - sw level en 9 disp-mux-hex clk - counter debouncing edge > > > reset detector Figure 5.10 Debouncing testing circuit. end i f ; when w a i t 0 - 2 => 95 db < = ’ I > ; i f s w = ’ 1 ’ then s t a t e - n e x t <= o n e ; e l s e i f m - t i c k = ’ l J then s t a t e - n e x t <= w a i t 0 - 3 ; end i f ; end i f ; when w a i t 0 - 3 = > db < = ’ I > ; 105 i f s w = ’ 1 ’ then s t a t e - n e x t <= o n e ; e l s e i f m - t i c k = ’ l ’ then s t a t e - n e x t <= z e r o ; I10 end i f ; end i f ; end c a s e ; end p r o c e s s ; 11s end a r c h ; 5.3.3 Testing circuit We use a bounce counting circuit to verify operation of the rising-edge detector and the debouncing circuit. The block diagram is shown in Figure 5.10. The input of the verification circuit is from a pushbutton switch. In the lower part, the signal is first fed to the debouncing circuit and then to the rising-edge detector. Therefore, a one-clock-cycle tick is generated each time the button is pressed and released. The tick in turn controls the enable input of an 8-bit counter, whose content is passed to the LED time-multiplexing circuit and shown on the left two digits of the prototyping board’s seven-segment LED display. In the upper part, the input signal is fed directly to the edge detector without the debouncing circuit, and the number is shown on the right two digits of the prototyping board’s seven-segment LED display. The bottom counter thus counts one desired 0-to- 1 transition as well as the bounces.

Debouncing Circuit – Exercise sw : input from slide switches or push Re-design the debouncer using a buttons. 20ms timer tick_20ms : input from a timer with 20ms period. timer can be controller by sw input.

Loop Statements

For-Loop Statements – – Count number of ‘0’ in the input library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity countzeros is port(a : in std_logic_vector(7 downto 0); Count : out std_logic_vector(2 downto 0) ); end countzeros; 55

architecture behavior of countzeros is signal zeros: std_logic_vector(2 downto 0); begin process (a, zeros) begin zeros <= "000"; for i in 7 downto 0 loop -- bounds must if (a(i) = ’0’) then -- be constants zeros <= zeros + 1; end if; end loop; Count <= zeros; end process; end behavior; 56

Combinational loop 57

Another Example shreg <= shreg (6 downto 0) & SI; for i in 0 to 6 loop shreg(i+1) <= shreg(i); end loop; shreg(0) <= SI; 58

Another Example for i in 0 to 6 loop shreg(i+1) <= shreg(i); end loop; for i in 0 to 6 loop shreg(1) <= shreg(1); … shreg(7) <= shreg(7); end loop; 59

While Loop Statement process (A) variable I : integer range 0 to 4; begin Z <= "0000"; I := 0; while (I <= 3) loop if (A = I) then Z(I) <= '1'; end if; I := I + 1; end loop; end process; 60

Alternative Coding Styles by Dr. Chu (to be used with caution)

Traditional Coding Style process(clock, reset) Inputs Next State function Next State clock State Present State reset Register concurrent Mealy Output Moore Output statements function function Mealy Outputs Moore Outputs

Alternative Coding Style 1 Process(Present State, Inputs) Inputs Next State function Next State Process(clock, reset) clock State Present State reset Register Process(Present Process(Present State) State, Inputs) Mealy Output Moore Output function function Mealy Outputs Moore Outputs

Alternative Coding Style 2 Process(Present State,Inputs) Process(clk, reset)

Backup

Hardware Design with RTL VHDL Interface Pseudocode Datapath Controller Block State diagram Block diagram or ASM chart diagram VHDL code VHDL code VHDL code 66

Algorithmic State Machine (ASM) Charts 67

Algorithmic State Machine Algorithmic State Machine – representation of a Finite State Machine suitable for FSMs with a larger number of inputs and outputs compared to FSMs expressed using state diagrams and state tables. 68

Elements used in ASM charts (1) State name Output signals 0 (False) 1 (True) Condition or actions expression (Moore type) (a) State box (b) Decision box Conditional outputs or actions (Mealy type) (c) Conditional output box 69

State Box ➺ A state box represents a state. ➺ Equivalent to a node in a state diagram or a row in a state table. State name ➺ Contains register transfer actions or output signals Output signals ➺ Moore-type outputs are listed inside of or actions the box. (Moore type) ➺ It is customary to write only the name of the signal that has to be asserted in the given state, e.g., z instead of z<=1. ➺ Also, it might be useful to write an action to be taken, e.g., count <= count + 1, and only later translate it to asserting a control signal that causes a given action to take place (e.g., enable signal of a counter). 70

Decision Box ➺ A decision box indicates that a given condition is to be 0 (False) 1 (True) Condition tested and the exit path is to expression be chosen accordingly. ➺ The condition expression may include one or more inputs to the FSM. 71

Conditional Output Box ➺ A conditional output box d enotes output signals that Conditional outputs are of the Mealy type. or actions (Mealy type) ➺ The condition that determines whether such outputs are generated is specified in the decision box. 72

ASMs Representing Simple FSMs ➺ Algorithmic state machines can model both Mealy and Moore Finite State Machines ➺ They can also model machines that are of the mixed type. 73

Moore FSM – Example 2: State diagram Reset w = 1 ⁄ ⁄ w = 0 A z = 0 B z = 0 w = 0 w = 0 w = 1 ⁄ C z = 1 w = 1 74

Moore FSM – Example 2: State Table Next state Output Present z state w = 0 w = 1 A A B 0 B A C 0 C A C 1 75

ASM Chart for Moore FSM – Example 2 Reset Reset A A 0 0 w w 1 1 B B 0 0 w w 1 1 C C z z 0 0 1 1 w w 76

Example 2: VHDL Code (1) entity entity simple is is port port ( clock : in in STD_LOGIC; resetn : in in STD_LOGIC; w : in in STD_LOGIC; z : out out STD_LOGIC); end end simple ; architecture architecture Behavior of of simple is is type type State_type IS (A, B, C) ; signal signal state : State_type ; begin begin process process ( resetn, clock ) begin begin if if resetn = '0' then then state <= A ; elsif elsif rising_edge rising_edge (Clock) then then 77

Example 2: VHDL Code (2) Reset Reset case case state is is when A => when if if w = '0' then then A A state <= A ; else else state <= B ; 0 0 end if ; end if w w 1 1 when B => when if w = '0' then if then B B state <= A ; else else state <= C ; end if ; end if 0 0 w w when C => when 1 1 if w = '0' then if then state <= A ; C C else else z z state <= C ; end if ; end if end case ; end case 0 0 1 1 w w 78

Example 2: VHDL Code (3) Reset Reset END IF END IF ; A A END PROCESS END PROCESS ; z <= '1' when when state = C else else 0 0 '0’; w w 1 1 END Behavior END Behavior ; B B 0 0 w w 1 1 C C z z 0 0 1 1 w w 79

Mealy FSM – Example 3: State Diagram Reset ⁄ w = 1 z = 0 A B ⁄ ⁄ w = 0 z = 0 w = 1 z = 1 ⁄ w = 0 z = 0 80

ASM Chart for Mealy FSM – Example 3 R e s e t A Reset ⁄ w = 1 z = 0 0 w A B 1 ⁄ ⁄ w = 0 z = 0 w = 1 z = 1 ⁄ w = 0 z = 0 B z 0 1 w 81

Example 3: VHDL Code (1) entity entity Mealy is is PORT ( clock : IN STD_LOGIC; resetn : IN STD_LOGIC; w : IN STD_LOGIC; z : OUT STD_LOGIC); end end Mealy; architecture architecture Behavior of of Mealy is is type State_type is type is (A, B) ; signal signal state: State_type ; begin begin process process (resetn, clock) begin begin if if resetn = '0' then then state<= A ; elsif elsif rising_edge rising_edge (clock) then then 82

Example 3: VHDL Code (2) case case state is is when when A => if if w = '0' then then state<= A ; else else Reset state<= B ; ⁄ w = 1 z = 0 end if end if ; when when B => if w = '0' then if then A B state<= A ; ⁄ ⁄ w = 0 z = 0 w = 1 z = 1 else else ⁄ w = 0 z = 0 state<= B ; end if ; end if end case ; end case end if; end if; end process; end process; 83

Example 3: VHDL Code (3) z <= '1' when when (y = B) and and (w=‘1’) else else '0’; end architecture end architecture Behavior ; Reset ⁄ w = 1 z = 0 A B ⁄ ⁄ w = 0 z = 0 w = 1 z = 1 ⁄ w = 0 z = 0 84

Case Study 1 Arbiter

Arbiter – Interface reset g1 r1 Arbiter r2 g2 g3 r3 clock

Arbiter – FSM r r r r r r 1 1 2 2 3 3 Reset Reset Idle Idle r r r r 1 1 1 1 ⁄ ⁄ gnt1 g gnt1 g = = 1 1 1 1 r r r r r r r r 1 1 2 2 1 1 2 2 ⁄ ⁄ gnt2 g gnt2 g = = 1 1 2 2 r r r r r r r r r r 2 2 3 3 1 1 2 2 3 3 ⁄ ⁄ gnt3 g gnt3 g = = 1 1 3 3 r r 3 3

Arbiter – VHDL Code ENTITY arbiter IS PORT(Clock, Resetn : IN STD_LOGIC ; r : IN STD_LOGIC_VECTOR(1 TO 3); g : OUT STD_LOGIC_VECTOR(1 TO 3)); END arbiter; ARCHITECTURE Behavior OF arbiter IS TYPE State_type IS (Idle, gnt1, gnt2, gnt3); SIGNAL state: State_type; begin 88

Arbiter – VHDL Code (cont’d) PROCESS(Resetn, Clock) BEGIN IF Resetn = '0' THEN state <= Idle ; ELSIF (Clock'EVENT AND Clock = '1') THEN CASE state IS WHEN Idle => IF r(1) = '1' THEN state <= gnt1 ; ELSIF r(2) = '1' THEN state <= gnt2 ; ELSIF r(3) = '1' THEN state <= gnt3 ; ELSE state <= Idle ; END IF ; WHEN gnt1 => IF r(1) = '1' THEN state <= gnt1 ; ELSE state <= Idle ; END IF ; -- continue on the next slide 89

Arbiter – VHDL Code (cont’d) WHEN gnt2 => IF r(2) = '1' THEN state <= gnt2 ; ELSE state <= Idle ; END IF ; WHEN gnt3 => IF r(3) = '1' THEN state <= gnt3 ; ELSE state <= Idle ; END IF ; END CASE ; END IF ; END PROCESS ; -- continue on the next slide 90

Arbiter – VHDL Code (cont’d) -- output function g(1) <= '1' WHEN state = gnt1 ELSE '0’; g(2) <= '1' WHEN state = gnt2 ELSE '0’; g(3) <= '1' WHEN state = gnt3 ELSE '0’; END architecture Behavior ; 91

Control Unit Example: Arbiter (1) reset g1 r1 Arbiter r2 g2 g3 r3 clock 92

Control Unit Example: Arbiter (2) 000 Reset Idle 0-- 1-- ⁄ gnt1 g = 1 1 1-- -0- 01- ⁄ gnt2 g = 1 2 -1- --0 001 ⁄ gnt3 g = 1 3 --1 93

Control Unit Example: Arbiter (3) r r r r 2 r 2 r 1 1 3 3 Reset Reset Idle Idle r r r r 1 1 1 1 ⁄ ⁄ gnt1 g gnt1 g = = 1 1 1 1 r r r r r r r r 1 1 2 2 1 1 2 2 ⁄ ⁄ gnt2 g gnt2 g = = 1 1 2 2 r r r r r r r r 2 r 2 r 2 2 3 3 1 1 3 3 ⁄ ⁄ gnt3 g gnt3 g = = 1 1 3 3 r r 3 3 94

ASM Chart for Control Unit - Example 4 Reset Reset Idle Idle 1 1 r r 1 1 gnt1 gnt1 1 1 0 0 0 0 g g 1 1 r r 1 1 1 1 r r 2 2 1 1 0 0 gnt2 gnt2 0 0 g g 2 2 r r 2 2 0 0 1 1 r r 3 3 1 1 gnt3 gnt3 0 0 g g 3 3 r r 3 3 95

Example 4: VHDL Code (1) ENTITY arbiter IS PORT(Clock, Resetn : IN STD_LOGIC ; r : IN STD_LOGIC_VECTOR(1 TO 3); g : OUT STD_LOGIC_VECTOR(1 TO 3)); END arbiter; ARCHITECTURE Behavior OF arbiter IS TYPE State_type IS (Idle, gnt1, gnt2, gnt3); SIGNAL state: State_type; begin 96

Example 4: VHDL code (2) PROCESS(Resetn, Clock) BEGIN IF Resetn = '0' THEN state <= Idle ; ELSIF (Clock'EVENT AND Clock = '1') THEN CASE state IS WHEN Idle => IF r(1) = '1' THEN state <= gnt1 ; ELSIF r(2) = '1' THEN state <= gnt2 ; ELSIF r(3) = '1' THEN state <= gnt3 ; ELSE state <= Idle ; END IF ; WHEN gnt1 => IF r(1) = '1' THEN state <= gnt1 ; ELSE state <= Idle ; END IF ; -- continue on the next slide 97

Example 4: VHDL code (3) WHEN gnt2 => IF r(2) = '1' THEN state <= gnt2 ; ELSE state <= Idle ; END IF ; WHEN gnt3 => IF r(3) = '1' THEN state <= gnt3 ; ELSE state <= Idle ; END IF ; END CASE ; END IF ; END PROCESS ; -- continue on the next slide 98

Example 4: VHDL code (3) g(1) <= '1' WHEN y = gnt1 ELSE '0’; g(2) <= '1' WHEN y = gnt2 ELSE '0’; g(3) <= '1' WHEN y = gnt3 ELSE '0’; END architecture Behavior ; 99

ASM Summary • ASM (algorithmic state machine) chart – Flowchart-like diagram – Provides the same info as a state diagram – More descriptive, better for complex description – ASM block • One state box • One or more optional decision boxes: with T (1) or F (0) exit path • One or more conditional output boxes: for Mealy output 100