CDA 4253 FPGA System Design PicoBlaze Interface Hao Zheng Comp Sci - PowerPoint PPT Presentation

CDA 4253 FPGA System Design PicoBlaze Interface Hao Zheng Comp Sci & Eng U of South Florida

Required Reading • P. Chu, FPGA Prototyping by VHDL Examples Chapter 16, PicoBlaze I/O Interface Chapter 17, PicoBlaze Interrupt Interface Xilinx PicoBlaze User Guide (UG 129) Chapter 4 & 6 2

Input InstrucCons INPUT sX, KK PORT_ID <= KK direct sX <= IN_PORT kk is the address of a peripheral. INPUT sX, (sY) PORT_ID <= sY indirect sX <= IN_POR T sY stores address of a peripheral. 3

Input OperaCon and FPGA Interface FPGA Logic PicoBlaze Microcontroller 8 D Q IN_PORT[7:0] Register sX m READ_STROBE Register sY or PORT_ID[7:0] Literal kk n 8 UG129_c6_01_052004 4

Input InstrucCons: Timing Diagram 1 2 3 4 0 CLK INSTRUCTION[17:0] INPUT s0,(s7) Contents of PORT_ID[7:0] register s7 IN_PORT[7:0] READ_STROBE Captured Value from Register s0 IN_PORT[7:0] UG129_c6_02_060404 5

Four ConCnuous-Access Ports 6

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Output InstrucCons OUTPUT sX, KK PORT_ID <= KK direct OUT_PORT <= sX OUTPUT sX, (sY) PORT_ID <= sY indirect OUTPUT <= sX write_strobe is asserted in the 2 nd cycle of an output instrucOon. • Used to noOfy target the validaty of the data on out_port • 8

Output Interfacing FPGA Logic PicoBlaze Microcontroller m Register sX OUT_PORT[7:0] D Q 8 WRITE_STROBE EN Register sY or PORT_ID[7:0] Literal kk 8 n UG129_c6_05_052004 Decode Logic 9

Output OperaCon and FPGA Interface Use WRITE_STROBE as the clock enable to capture output values in FPGA logic. 1 2 3 4 0 CLK INSTRUCTION[17:0] OUTPUT s0, 65 PORT_ID[7:0] 65 Contents of OUT_PORT[7:0] Register s0 WRITE_STROBE Captured Value from FPGA Register OUT_PORT[7:0] UG129_c6_06_060404 10

Output Decoding of Four Output Registers 11

369 OUTPUT PORT Figure 16.2 Output decoding of four output registers. Decoder Logic Truth table of a decoding circuit Table 16.1 input output write-strobe port -id (1) port-id( 0) en-d 0000 - - 0 000 0 1 0 1 0010 1 0 0100 1 1 1000 The decoder logic can be saved by using one-hot codes for port_id if the output ports are smaller than 8. 16.2.2 Output interface 12 The output interface between PicoBlaze and an output peripheral usually consists of a decoding circuit and necessary output buffers, which are normally an array of registers. The decoding circuit decodes the port id and generates an enable tick accordingly. After the output instruction, the data will be stored in the designated buffer. To illustrate the construction, let us consider a PicoBlaze interface with four output buffers. We assign 0016, OIl6, 0216, and 0316 as their port ids. Note that the six MSBs of the port addresses are identical and only two LSBs are needed to distinguish a port. The block diagram is shown in Figure 16.2. The key is the decoding circuit, whose function table is shown in Table 16.1. It is a 2-t0-2~ decoder. In the second clock cycle of an output instruction, write-strobe is asserted and 1 bit of the 4-bit en-d signal is asserted accordingly. The one-clock-cycle enable tick activates the corresponding output register to retrieve data from the out-port signal. The decoding timing diagram of the instruction output s o , 02

Timing Diagram of an Output InstrucCon output s0, 02 13

Simple Address Decoding for PORT_C D Q [2] Designs with <8 EN Output Components PORT_B D Q [1] EN PORT_A D Q [0] PicoBlaze Microcontroller EN IN_PORT[7:0] OUT_PORT[7:0] PORT_ID[7:0] READ_STROBE WRITE_STROBE UG129_c6_07_052004 14

ADDRESS 000 Interrupt Flow main: 1 ENABLE INTERRUPT INPUT s0, 00 INTERRUPT 1. Enabled interrupts input 2 INPUT s1, 01 asserted. ADD s0, s1 OUTPUT s0, 00 2. An interrupt occurs 6 CALL critical_timing 3. Execute call 3FF JUMP main 4. Execute jump isr critical_timing: DISABLE INTERRUPT 5. Execute interrupt service rouOne (ISR) at isr ENABLE INTERRUPT RETURN 6. execute returni enable at isr: TEST s7, 02 the end of ISR, and 5 resume the normal 4 operaOon RETURNI ENABLE 3 ADDRESS 3FF JUMP isr 15

4 1 2 3 5 6 7 8 16

Interrupt Related InstrucCons RETURNI ENABLE PC <= STACK[TOS] ; TOS <= TOS – 1; I <= 1; C<= PRESERVED C; Z<= PRESERVED Z RETURNI DISABLE PC <= STACK[TOS] ; TOS <= TOS – 1; I <= 0; C<= PRESERVED C; Z<= PRESERVED Z ENABLE INTERRUPT I <=1; DISABLE INTERRUPT I <=0; 17

Interrupt Interface with a Single Event interrupt should hold high unOl interrupt_ack is asserted. 18

Interrupt Interface with Two Requests ISR reads in_port[1:0], decides which request should be served, and generate correct signal to clear the corresponding interrupt request FF. 19

Time-MulCplexed Seven Segment Display Data inputs 20

Time-MulCplexing Circuit 21

MulCplexing Circuit Based on PicoBlaze • mod-500 generates an interrupt every 5us. • ISR loads sseg[6:0] from memory and generates corresponding port ID for an[3:0] . 22