Field Programmable Gate Array - What is it? 2D array of logic blocks - PowerPoint PPT Presentation

May 07, 2023 •786 likes •850 views

Field Programmable Gate Array - What is it? 2D array of logic blocks surrounded by a interconnection matrix and I/O Fundamental Structure Altera Cyclone IV Programmable, but not in the usual sense Programmed with a bit file loaded into

Field Programmable Gate Array - What is it? ◮ 2D array of logic blocks surrounded by a interconnection matrix and I/O Fundamental Structure Altera Cyclone IV ◮ Programmable, but not in the usual sense ◮ Programmed with a bit file loaded into SRAM ◮ Internal SRAM holds the configuration for logic and interconnect ◮ Schematics are rarely used, HDLs mostly
FPGAs as compared to ASICs - Usage models ◮ ASIC ◮ Application Specific - does one thing - fixed circuit ◮ MPEG Decoder, Dolby Noise Reduction, MRI Image Processor ◮ Very cheap in very large volumes ◮ FPGA ◮ Extremely Flexible - can do many things - infinitely changeable ◮ uC, MPEG Decoder, digital signal processor,... ◮ Relatively expensive in even fairly large volumes
FPGAs as compared to ASICs - Architecture ◮ ASIC ◮ About 200 Predesigned (standard) cells: NOR, NAND, XOR ◮ Each cell chosen and sized by synthesis ◮ Very dense, very optimized design ◮ Full mask set needed, diffusion, contacts, wells,...everything ◮ Requires test circuitry insertion, test vector generation ◮ FPGA ◮ Combo logic via Logic Elements (LE) - SRAM memory lookup ◮ Prefabricated PLL, Embedded Memory, Embedded Multipliers ◮ Prefabricated interconnect fabric, clock trees, and I/O cells ◮ Fully tested at manufacture
FPGAs as compared to ASICs - Time and Cost ◮ ASIC ◮ Full mask set 1M $ (90nm) to 2M $ (40nm) dollars ◮ NRE 50-250K $ ◮ Sign-off to 1st article 2-3 months ◮ Re-spin, 2-3 months total, 100’s of K $ , loss of market window ◮ Expensive tool-set; Takes a minimum of 1M $ to play the game ◮ 1 seat of DC shell is about 150-200K $ ◮ FPGA ◮ Parts are prefabricated, no NRE ◮ Respin in one day or less ◮ Tool-set, couple of K $ at most, many are free ◮ No test insertion or vectors, fully tested at manufacture
FPGA Relative advantages/disadvantages ◮ FPGA Advantages ◮ Time to market (TTM): 1 month ≈ 10% market share ◮ Flexibility: one part reused for many projects ◮ Risk: Bugs are easier to find, simple and fast to fix ◮ Capacity of parts continues to increase quickly ◮ FPGA disadvantages ◮ 40x the area of ASIC ◮ 3-4x the delay of ASIC ◮ 12x the power of ASIC (Kuon and Rose, FPGA 2006)

Recommend

Field Programmable Gate Arrays by Ketil Red Field Programmable Gate Array Integrated

A brief introduction to Field Programmable Gate Arrays by Ketil Red Field Programmable Gate Array Integrated circuit including a matrix of general-purpose programmable logic I I I I I I I I I I I I I I I I I I I I

439 views • 14 slides

WWW.FPGA What is an FPGA? Field Programmable Gate Array Introduction to FPGA designs

WWW.FPGA What is an FPGA? Field Programmable Gate Array Introduction to FPGA designs Generic logic cells + Programmable switches Why do we use it? High performance & Flexible Shorter time to market Joachim Rodrigues

311 views • 8 slides

Regulatory Guidance on the Use of Field Programmable Gate of Field Programmable Gate Arrays in

Regulatory Guidance on the Use of Field Programmable Gate of Field Programmable Gate Arrays in the U.S. October 13, 2015 Steven A. Arndt, Ph.D., P.E. Office of Nuclear Reactor Regulation The views expressed in this presentation are solely

542 views • 23 slides

Seizure Prediction using Hilbert Huang Transform on Field Programmable Gate Array Dilranjan S.

Introduction Methodology Results and Discussion Seizure Prediction using Hilbert Huang Transform on Field Programmable Gate Array Dilranjan S. Wickramasuriya Lakshitha P. Wijesinghe Sudaraka Mallawaarachchi University of Moratuwa December 16,

442 views • 23 slides

Tips about an FPGA 02/09/2018 J.C. special topic FPGA ( field-programmable gate array ) FPGA :

Tips about an FPGA 02/09/2018 J.C. special topic FPGA ( field-programmable gate array ) FPGA : An integrated circuit (IC) designed to be configured by customer or designer after manufacturing -- Developed in ~80s -- Widely used (customer

303 views • 7 slides

NEPP Update of Independent Single Event Upset Field Programmable Gate Array Testing Melanie

https://ntrs.nasa.gov/search.jsp?R=20170005805 2017-12-10T00:44:12+00:00Z NEPP Update of Independent Single Event Upset Field Programmable Gate Array Testing Melanie Berg, AS&D Inc. in support of the NEPP Program and NASA/GSFC

682 views • 50 slides

Field Programmable Gate Array (FPGA) Radiation Data: All Data are Not Equal Kenneth A. LaBel

Unclassified Field Programmable Gate Array (FPGA) Radiation Data: All Data are Not Equal Kenneth A. LaBel ken.label@nasa.gov Co-Manager, NASA Electronic Parts and Packaging (NEPP) Program Melanie D. Berg melanie.d.berg@nasa.gov ASRC Space

452 views • 22 slides

NASA Electronic Parts and Packaging Field Programmable Gate Array Single Event Effects Test

NASA Electronic Parts and Packaging Field Programmable Gate Array Single Event Effects Test Guideline Update Melanie Berg 1 , Kenneth LaBel 2 , Melanie.D.Berg@NASA.gov 1.AS&D in support of NASA/GSFC 2. NASA/GSFC P resented by Melanie Berg

442 views • 21 slides

The Next Generation of Cryptanalytic Hardware FPGAs (Field Programmable Gate Arrays) allow custom

The Next Generation of Cryptanalytic Hardware FPGAs (Field Programmable Gate Arrays) allow custom silicon to be implemented easily. The result is a chip that can be built specifically for cracking passwords. This presentation focuses on

784 views • 55 slides

PicoCrack: The Art of Efficient Cracking FPGAs (Field Programmable Gate Arrays) allow custom

PicoCrack: The Art of Efficient Cracking FPGAs (Field Programmable Gate Arrays) allow custom silicon to be implemented easily. The result is a chip that can be built specifically for cracking passwords. This presentation focuses on uncovering

606 views • 47 slides

USING FIELD PROGRAMMABLE GATE ARRAYS IN A BEOWULF CLUSTER Matthew J. Krzych Naval Undersea

USING FIELD PROGRAMMABLE GATE ARRAYS IN A BEOWULF CLUSTER Matthew J. Krzych Naval Undersea Warfare Center Approved for Public Release, Distribution Unlimited. Sponsor DARPA - Advanced Technology Office Robust Passive Sonar Program

728 views • 13 slides

Introduction by Erol Seke For the course Introduction to VHDL ESKEHR OSMANGAZI

Introduction by Erol Seke For the course Introduction to VHDL ESKEHR OSMANGAZI UNIVERSITY What are FPGAs ? Field Programmable Gate Array : We have a bunch of digital circuit primitives with user programmable connections designer

884 views • 44 slides

Unit 18 Field Programmable Gate Arrays (FPGAs) Implementing Logic Functions with Memories 18.2

18.1 Unit 18 Field Programmable Gate Arrays (FPGAs) Implementing Logic Functions with Memories 18.2 HARDWARE IMPLEMENTATION TARGETS 18.3 Processing Logic Approaches Application Recall HW/SW designs sit on a continuum Specific

660 views • 32 slides

Unit 18 Field Programmable Gate Arrays (FPGAs) HARDWARE IMPLEMENTATION Implementing Logic

18.1 18.2 Unit 18 Field Programmable Gate Arrays (FPGAs) HARDWARE IMPLEMENTATION Implementing Logic Functions with Memories TARGETS 18.3 18.4 Processing Logic Approaches Progression of HW Logic Density Recall HW/SW designs sit on a

462 views • 8 slides

ROMs, PLAs and FPGAs October 5, 2006 Typeset by Foil T EX Why Programmable Logic?

ROMs, PLAs and FPGAs October 5, 2006 Typeset by Foil T EX Why Programmable Logic? Programmable logic technologies: Read-Only Memory (ROM) Programmable Logic Array (PLA) Programmable Array Logic (PAL) Field Programmable

283 views • 13 slides

Lab Field-Programmable Gate Arrays Initial Meeting Sebastian Schller University of Bonn

Lab Field-Programmable Gate Arrays Initial Meeting Sebastian Schller University of Bonn Institute for Computer Science VI, Technical Computer Science July 26th, 2019 Overview Design hardware implementation for Lucas-Kanade Optical Flow.

274 views • 8 slides

High-Speed Computing & Co-Processing with FPGAs FPGAs (Field Programmable Gate Arrays) are

High-Speed Computing & Co-Processing with FPGAs FPGAs (Field Programmable Gate Arrays) are slowly becoming more and more advanced and practical as high-speed computing platforms. In this talk, David will provide an in-depth introduction into

478 views • 43 slides

Introduction to Field Programmable Gate Arrays Lecture 2/3 CERN Accelerator School on Digital

Introduction to Field Programmable Gate Arrays Lecture 2/3 CERN Accelerator School on Digital Signal Processing Sigtuna, Sweden, 31 May 9 June 2007 Javier Serrano, CERN AB-CO-HT Outline Digital Signal Processing using FPGAs

1.29k views • 43 slides

S OFTWARE Defined Networking (SDN) has been proposed Field Programmable Gate Array (FPGA)

IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, VOL. 27, NO. 1, JANUARY 2016 197 High-Performance and Dynamically Updatable Packet Classification Engine on FPGA Yun R. Qu, Member, IEEE and Viktor K. Prasanna, Fellow, IEEE Abstract

351 views • 13 slides

A Unified Program for Modifying Built-In Self-Test Architectures for Xilinx Field Programmable

A Unified Program for Modifying Built-In Self-Test Architectures for Xilinx Field Programmable Gate Arrays Neil Da Cunha Auburn University November 2 nd , 2011 Committee Members: Charles E. Stroud, Chair, Professor of Electrical and Computer

524 views • 34 slides

An introduction to FPGA-based acceleration of neural networks Marco Pagani 1 What is an FPGA?

An introduction to FPGA-based acceleration of neural networks Marco Pagani 1 What is an FPGA? Field-programmable gate array (FPGA) are integrated circuits designed to be con fi gured after manufacturing for implementing arbitrary logic

429 views • 15 slides

Random Number Generator using FPGA David P erez Mart nez Centro de Investigaci on en

Random Number Generator using FPGA David P erez Mart nez Centro de Investigaci on en Computaci on - IPN Introduction A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer.

256 views • 9 slides

Gate B Gate B Gate B Gate D Gate D Gate D Gate E Gate E Gate E Ferry Plaza Ferry Plaza

Novato | S a n Vallejo % ' & ( 29 780 Benicia P a b l o | Hercules B a y 101 | 4 San Rafael M A R I N Pinole | % ( ' & Martinez 242 Concord Richmond 80 Pleasant Hill % & ( ' Larkspur

551 views • 11 slides

Programable Logic Devices In the 1970s programmable logic circuits called programmable logic

Programable Logic Devices In the 1970s programmable logic circuits called programmable logic device (PLD) was introduced. They are based on a structure with an AND- OR array that makes it easy to implement SOP expression William Sandqvist

830 views • 64 slides