Unit 18 Field Programmable Gate Arrays (FPGAs) Implementing Logic - PowerPoint PPT Presentation

18.1 Unit 18 Field Programmable Gate Arrays (FPGAs) Implementing Logic Functions with Memories

18.2 HARDWARE IMPLEMENTATION TARGETS

18.3 Processing Logic Approaches • Application Recall HW/SW designs sit on a continuum Specific Hardware • Suppose I want to implement: F = (X+Y)*(A+B) (no software) • Custom Hardware (Faster, Less Power) Flexibility, Design Time Computing System – Logic that directly implements a specific task Performance Continuum – Example above may use separate adders and a Cost multiplier unit • General Purpose (GP) Processor/Microcontroller (Design Time, Cost) – Logic designed to execute SW instructions – Provides basic processing resources that are reused by Processor each instruction Executing Software • What if I want to perform: (X*Y) + (A*B) – What's easiest to redesign? Data in Mem. CPU control Instruc. X + Store Y F (Adder) * ADD T,X,Y + * ADD S,A,B A + MUL F,T,S Proc B (Adder) GP Proc. Implementation Custom HW Implementation of (X+Y)*(A+B)

18.4 Progression of HW Logic Density • Our ability to design hardware components with greater numbers of gates/transistors has increased exponentially • Small Scale Integrated (SSI) Circuits – 1960’s and 1970’s – A few gates on a chip (74LS00 has 4 NAND gates) • Medium Scale Integrated (MSI) Circuits – 1970’s – Around a hundred gates per chip (4-bit adder) • Large Scale Integrated (LSI) Circuits • Very Large Scale Integrated (VLSI) Circuits – 100’s of millions of gates

18.5 ASICs • Application Specific Integrated Circuits (ASICs) is another name for a typical "chip" • Computer engineers determine the gates and their interconnection that performs a specific task/application – Start with high level "behavioral" description – Use CAD software tools to refine that to logic gates – Use CAD software tools to refine that to transistors and where each should be located on the surface of the chip and how they should be wired together In an ASIC design, a unique chip will be – From there the chip is fabricated and mass-produced manufactured that implements our design at • Design process is expensive, and once which point the HW design is fixed & cannot fabricated the design cannot be changed (but it be changed (example: is fast and uses less power) Pentium, etc.)

18.6 ASICs

18.7 Motivation for Reconfigurable Logic • Could we get some of the benefits of both hardware (speed/power) AND software (flexible/reusable) • Yes…enter Field Programmable Gate Arrays (FPGAs) – Has prebuilt, generic hardware constructs FPGA’s have “logic resources” on them that that can be configured and interconnected we can configure to based on one design and then reconfigured implement our specific design. We can then and interconnected later for another design reconfigure it to • Let's learn more about the secret implement another design ingredient to FPGAs…memories! Computing System Continuum Application Microcontroller/Processor Specific Hardware Executing Software (no software / custom chip) Reconfigurable Hardware; FPGAs

18.8 Where are FPGAs Used • Datacenters – Bing search engine – Real-time data analytics – Compression and encryption – High-frequency trading • Robots and Rovers – JPL and the Mars Rovers • Telecom • Aerospace

18.9 USING MEMORIES TO BUILD COMBINATIONAL CIRCUITS

18.10 Dimensions and Operations MEMORY BASICS

18.11 Memories • Memories store (write) and retrieve (read) data – Read- Only Memories (ROM’s): Can only retrieve data (contents are initialized and then cannot be changed) – Read- Write Memories (RWM’s): Can retrieve data and change the contents to store new data

18.12 ROM’s ROM • Memories are just tables of data with rows and A 0 0 0 1 1 0 A 1 columns 1 0 1 0 1 A 2 • When data is read, one 0 1 0 0 2 entire row of data is read 0 1 1 1 3 out 1 1 0 1 4 • The row to be read is Address 5 1 0 0 0 Inputs 6 0 1 1 0 selected by putting a 7 binary number on the 1 0 1 1 address inputs Data D 3 D 2 D 1 D 0 Outputs

18.13 ROM’s ROM • Example 0 A 0 – Address = 4 10 = 100 2 is 0 0 1 1 0 0 A 1 provided as input 1 0 1 0 1 1 A 2 – ROM outputs data in that 0 1 0 0 2 row (1101 bin.) 0 1 1 1 3 1 1 0 1 4 Address: 5 1 0 0 0 100 2 = 4 10 6 0 1 1 0 7 1 0 1 1 D 3 D 2 D 1 D 0 Data: Row 4 is 1 1 0 1 output

18.14 Memory Dimensions ROM • Memories are named by A 0 … their dimensions: 0 1 0 A 1 1 0 – Rows x Columns 1 … 0 0 A n-1 2 • n rows and m columns => n x m ROM . . • n rows => log 2 n address bits . …or… 2 n -2 0 0 2 k rows => k address bits 1 1 2 n -1 • m cols => m data outputs D m-1 D 0

18.15 RWM’s 8x4 RWM • Writable memories provide a set of data A 0 0 0 1 1 0 A 1 inputs for write data (as 1 0 1 0 1 A 2 opposed to the data 0 1 0 0 2 Address outputs for read data) Inputs 0 1 1 1 3 DI 0 • A control signal R/W 1 1 0 1 4 DI 1 (1=READ / 0 = WRITE) is 5 1 0 0 0 DI 2 Data provided to tell the DI 3 6 0 1 1 0 Inputs memory what operation 7 1 0 1 1 R/W the user wants to perform Data DO 3 DO 2 DO 1 DO 0 Outputs

18.16 RWM’s 8x4 RWM • Write example 1 A 0 – Address = 3 10 = 011 2 0 0 1 1 0 1 A 1 – DI = 12 10 = 1100 2 1 0 1 0 1 0 A 2 – R/W = 0 => Write op. 0 1 0 0 2 Address 1 1 0 0 Inputs • Data in row 3 is 0 1 1 1 3 0 DI 0 overwritten with the new 1 1 0 1 4 0 DI 1 value of 1100 2 . 5 1 0 0 0 1 DI 2 Data 1 DI 3 6 0 1 1 0 Inputs 7 1 0 1 1 R/W 0 DO 3 DO 2 DO 1 DO 0 R/W Data ? ? ? ? Outputs

18.17 Look- up tables… USING MEMORIES TO BUILD COMBINATIONAL FUNCTIONS

18.18 Memories as Look-Up Tables • One major application of memories in digital design is to use them as LUT’s (Look -Up Tables) to implement logic functions – This is the core technology used by FPGAs (Field- Programmable Gate Arrays) • Idea : Use a memory to hold the truth table of a function and feed the inputs of the function to the address inputs to "look-up" the answer

18.19 Implementing Functions w/ Memories 8x1 Memory 8x1 Memory Z A 0 0 A 0 1 1 0 0 X Y Z F Y A 1 1 A 1 0 0 0 0 0 1 1 1 X A 2 1 A 2 0 0 1 0 1 1 2 2 X,Y,Z inputs 0 1 0 1 “look up” 1 1 3 3 the correct X 0 1 1 1 A 0 Y answer A 1 0 0 4 4 D 0 F Z A 2 1 0 0 0 8x1 Mem. 5 0 5 0 1 0 1 0 6 6 0 0 1 1 0 0 7 7 1 1 1 1 1 1 X D 0 D 0 Arbitrary F Logic Y Z Function F 0 Use a memory with the same dimensions as 'output' side of the truth table. It's almost TOO easy.

18.20 Implementing Functions w/ Memories 8x2 Memory 8x2 Memory Z A 0 1 A 0 0 0 0 0 0 0 X Y Z C S Y A 1 0 A 1 0 1 0 1 0 0 0 0 0 1 1 X A 2 1 A 2 0 0 1 0 1 0 1 0 1 2 2 0 1 0 0 1 1 0 1 0 3 3 1 0 0 1 1 0 1 0 1 4 4 1 0 0 0 1 5 1 0 5 1 0 1 0 1 1 0 6 6 1 0 1 0 1 1 0 1 0 7 7 1 1 1 1 1 1 1 1 1 D 1 D 0 D 1 D 0 Multi-bit function (One's count) 1+0+1 = 10 C S 1 0 Use a memory with the same dimensions as 'output' side of the truth table. It's almost TOO easy.

18.21 3-bit Squaring Circuit • Q: What size memory Inputs Outputs would you use to build B=A 2 A A 2 A 1 A 0 B 5 B 4 B 3 B 2 B 1 B 0 our 3-bit squaring 0 0 0 0 0 0 0 0 0 0 0 circuit? 1 0 0 1 0 0 0 0 0 1 1 • A: 8x6 memory 2 0 1 0 0 0 0 1 0 0 4 • Q: What would you 3 0 1 1 0 0 1 0 0 1 9 connect to the address 4 1 0 0 0 1 0 0 0 0 16 inputs of the memory? 5 1 0 1 0 1 1 0 0 1 25 • A: A[2:0] 6 1 1 0 1 0 0 1 0 0 36 • Q: What bits would you 7 1 1 1 1 1 0 0 0 1 49 program into row 5 of Memory Contents to the memory? build 3-bit Squaring Circuit • A: 011001 (i.e. 25 = 5 2 )

18.22 4x4 Multiplier Example Determine the dimensions of Y0 A0 ROM the memory that would be Y1 A1 necessary to implement a 0 0 0 0 0 0 0 0 Y2 A2 0 4x4-bit unsigned multiplier Y3 A3 with inputs X[3:0] and Y[3:0] 2 0 0 0 0 0 0 0 0 X0 A4 and outputs P[??:0] X1 A5 Question: How many bits 0 0 0 0 0 1 0 0 X2 A6 20 are needed for P? X3 A7 Question: What are the 0 0 0 0 1 1 1 0 39 contents of the numbered 20=00010100 rows? =0001*0100=4 ... Example: 39=00100111 =0010*0111=14 X 3 X 2 X 1 X 0 =0010 1 1 1 0 0 0 0 1 Y 3 Y 2 Y 1 Y 0 =0001 255 P = X * Y = 2 * 1 = 2 255=11111111 =1111*1111=225 = 00010 P7 P0

18.23 Implementing Functions w/ Memories • To implement a function w/ n-variables and m outputs • Just place the output truth table values in the memory • Memory will have dimensions: 2 n rows and m columns – Still does not scale terribly well (i.e. n-inputs requires memory w/ 2 n outputs) – But it is easy and since we can change the contents of memories it allows us to create "reconfigurable" logic – This idea is at the heart of FPGAs

18.24 FPGAS