El. devices fabrication (2) [Hastings]
Production of silicon Crystal growth - starting from electronic grade Si, obtained by distillation from metallurgical grade Si - Czochralski method -> ingots (height ~ 1m) Then: - cut -> wafers (diam. 6 - 12 inches, 0.150-0.300 mm) - polishing (mechanical (abrasive) + chemical) Orientation (100) or (111)
Oxide growth/deposition - Oxide: SiO 2 - easy growth/deposition - mechanically rugged; readily dissolves in HF - excellent isolator -> also for MOS Growth - - dry : Si + O 2 -> SiO 2 - wet (not so good (superficial charge) but faster): Si + 2H 2 O -> SiO 2 + 2H 2 - T ~ 1000 o C - thickness: ~ 2x wrt Si (see LOCOS later) Alternatively: deposition (not so good!). E.g.: - SiH 4 + 2NO 2 -> N 2 + 2H 2 O + SiO 2 This is an example of chemical vapor deposition (CVD)
Masks If selective processing is needed, a patterned material - can be used as a mask the patterning is done via photolithography (see later) - materials: - - low T : photoresist ( soft mask ) - high T : SiO 2 o Si 3 N 4 (hard mask), which, of course, are patterned using photoresist)
Photolithography (1/3) ◼ Photoresist (deposited via spinning) - negative (polymerize with UV) - positive (depolymerize with UV)
Photolithography (2/3) - Photomasks (reticles) - normally 5x or 10x (with stepper -> several or (photo)reticle exposures (each normally for more than one die ) - or, mask 5x or 10x -> stepped working plate -> only one exposure, 1x - very expensive; normally obtained via direct writing ( electron beam lithography )
Photolithography (3/3) Then, development (with organic solvents) to remove - the non-polymerized photoresist Then, after the selective processing (deposition or - etching) , the photoresist is removed - chemically (with solvents), or with - reactive ion etching ( ashing ): plasma with oxygen
Oxide removal - wet etching (with HF, isotropic) - dry etching (e.g. with reactive ion etching, e.g. trichloroethane + Ar; anisotropic -> better control on the widths)
Oxide… Reactive ion etching
LOCOS; silicon nitride LOCOS (local oxidation of silicon): selective growth of a very thick oxide: normally for field oxide For Si 3 N 4 : CVD 3SiH 4 +4NH 3 -> Si 3 N 4 +12H 2
Diffusions Diffusion: - (pre)deposition - drive(-in) T ~ 800-1250 o C Dopants: Si-p: B (B 2 H 6 ) Si-n: P (POCl 3 , PH 3 ), As, Sb Poor horizontal control: isotropic process! E.g.: 4POCl 3 +3O 2 -> 2P 2 O 5 +6Cl 2 P 2 O 5 builds a glass on Si 2P 2 O 5 +5Si -> 4P+5SiO 2
Diffusions Main parameters of the dopant: - diffusion coeff. - solid solubility NB: As, Sb have low diff. coeff.
Diffusions Ion implantation (actually, it is not a diffusion...) ◼ Ions are launched into the silicon ◼ then, short annealing ( T ~ 800 o C) and, possibly, high T drive ◼ high T not needed (-> photoresist as mask) ◼ better control; expensive and slow ◼ self-alignment (apart from straggle and small diffusion) ◼ depth depends on V (and by the drive, if present)
Deposition of silicon (mono) To have a single crystal: epitaxy - (rare: liquid phase (with melted Si )) - low pressure chemical vapor deposition (LPCVD), SiH 2 Cl 2 -> Si + 2HCl (with H 2 as carrier), or SiCl 4 +2H 2 -> Si + 4HCl or SiH 4 -> Si + 2H 2 possibly with PH 3 o B 2 H 6 o AsH 3 to dope - slow (~1 m m/min) and expensive - T ~ 1100 o C
Deposition of silicon (polysilicon or “poly”) For polysilicon: CVD SiH 4 -> Si + 2H 2 e.g. on SiO 2 used - normally for MOS gates (withstands larger T wrt Al, and V T is better controlled) - also for resistors (instead of diffused resistors) - also as a layer for (short) routing apparatus similar to the one for epitaxy
Metallizations (1/3) Al deposition: - e.g via evaporation (this is an example of physical vapor deposition , PVD) Some % of Si in Al reduces the contact spiking (o emitter punchthrough ) Some % of Cu in Al reduces electromigration Patterning: - normal - lift-off (metal on the photoresist) On the contacts, Al dopes Si: - ok for Si-p - for Si-n, Si-n + is needed (see Schottky junction)
Metallizations (2/3) To improve lateral coverage: - reflow ( before Al): high T , with P and B added to SiO 2 - refractory barrier metals (Mo, W (tungsten), Ti) Deposited via sputtering (they melt at too large T for evaporation) Also reduce contact spiking (and electromigration) But have poor conductance -> sandwich with Al -> e.g.. refractory metal, and Al with Cu (Si not needed)
Metallizations (3/3) Silicides: Si + metal (PtSi, Pd 2 Si, TiSi …) - good ohmic contacts, or Shottky diodes; moreover - low resistivity -> for low resistivity poly ( clad poly ), e. g. for high speed MOS Ex of final sandwich: PtSi + refractory + Al with Cu ◼ Also poly layers are often called “ metallizations ”
And then... Between poly and metal1: multilevel oxide (MLO), with contact openings between metal1 and Si or Poly Between the various metals: interlevel oxide (ILO), with vias between the various metals Above all: protective overcoat (PO), or overglass , tipically Si 3 N 4 (more resistent than SiO 2 ), with openings for the pads
Assembly and testing Often made in another facility (easy step -> e.g. in the far east) Process control structures: transistors, R, C, contacts… Test dice: variants of the IC, or to test subcircuits… Test (wafer probing): of the wafer of each IC (t ~ s; yield ~ 80%)
Assembly… Then - cut - mounting on the leadframe (also for thermal exchange) - epoxy resin - soldering (also to have a substrate contact)
Assembly… Bonding (from bondpads to leadfingers ) - Normally, 1 mil gold wire and ball bonding - for Al: wedge bonding (similar, but the wire is snapped) - 10 per second!
Assembly… An IC with many leads...
Assembly… An IC with many leads...
Assembly… An IC with many leads...
Packaging In plastic (normally injected from the bottom)…
Packaging In plastic (normally injected from the bottom)…
Packaging ... or ceramic…
Finally… ◼ further tests ◼ final packaging (tubes, reels…)
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