Drive Strength Aware Cell Movement Techniques for Timing Driven - PowerPoint PPT Presentation

Drive Strength Aware Cell Movement Techniques for Timing Driven Placement Guilherme Flach, Mateus Fogaça, Jucemar Monteiro , Marcelo Johann and Ricardo Reis Universidade Federal do Rio Grande do Sul (UFRGS) - Brazil jucemar.monteiro@inf.ufrgs.br

Agenda Introduction Contributions Evaluation Metrics Late Timing-Driven Placement Techniques Early Timing-Driven Placement Techniques ABU Improvement Experimental Results Conclusion 2

Introduction

Introduction 4

Interconnection Characteristics 5

Path Characteristics Fixed Fixed 6

UPlacer 7

Early and Late Timing Violations Launch point Capture point Early Violation 8

Early and Late Timing Violations Launch point Capture point Early Late Violation Violation 9

Early and Late Timing Violations Launch point Capture point Early Late No Timing Violation Violation Violation 10

Contributions

Contributions Local-cell movements a local optimum solution 12

Contributions Local-cell movements a local optimum solution Cell Movement Improve timing by balancing wire capacitance and resistance 13

Evaluation Metrics

Metrics Driver Sensitivity Calculations X1 X4 X1 15

Metrics Driver Sensitivity Calculations X1 X4 X1 Direction of Cell Movement to minimize timing violation 16

Metrics Criticality = Worst Negative Slack(pin) Worst Negative Slack (circuit) 17

Metrics Criticality = Worst Negative Slack(pin) Worst Negative Slack (circuit) WNS(circuit) = 20 A WNS(A) = 14 WNS(B) = 6 B 18

Metrics Criticality = Worst Negative Slack(pin) Worst Negative Slack (circuit) WNS(circuit) = 20 A Criticality(A) = 0.7 Criticality(B) = 0.3 B 19

Metrics Centrality: Indirect measure of how many and how critical are the endpoints affected by a pin 1 A 9 B 20

Metrics Centrality: Indirect measure of how many and how critical are the endpoints affected by a pin 1 A 10 9 B 21

Metrics Centrality: Indirect measure of how many and how critical are the endpoints affected by a pin 7 = 0.7 x 10 1 A 7 10 3 9 B criticality(A) = 0.7 criticality(B) = 0.3 22

Late Optimization

Clustered Cell Movement For each critical cell N1 N2 N4 N3 24

Clustered Cell Movement Make clusters of topological neighbour cells N1 N2 N4 N3 25

Clustered Cell Movement Find the center of mass for the cluster N1 N2 N4 N3 26

Clustered Cell Movement Find new cluster position to minimize timing violations N1 N2 N4 N3 27

Clustered Cell Movement Move cells toward to new cluster center N1 N2 N4 N3 28

Buffer Balancing Goal delay delay Minimize segment delay by balancing driver/sink load and delay. displacement displacement 29

Buffer Balancing Assumptions and Formulation Elmore delay. Single driver/sink. Driver/sink won’t move. 30

Buffer Balancing Assumptions and Formulation Elmore delay. Single driver/sink. Driver/sink won’t move Analytical Formulation d 0 a d 1 d 0 a d 1 31

Cell Balancing Extension of buffer balancing movement 32

Cell Balancing Driver and Sink Driver Point Sink Point 33

Cell Balancing Analytical Formulation d 0 a d 1 driver point sink point 34

Cell Balancing New Cell Position Driver Point Sink Point 35

Load Optimization CS ● Critical nets ● Load Capacitance optimization D 36

Load Optimization CS ● Critical nets ● Load Capacitance optimization D ● Non critical sinks ● Move toward to its driver 37

Early Optimization 38

Skew Optimization ● Clock Skew Target ● Startpoint register ● Reduce local clock load capacitance and LCB FF resistance 39

Skew Optimization ● Clock Skew Target ● Startpoint register ● Reduce local clock load LCB capacitance and FF resistance ● Move closer to LCB 40

Iterative Cell Spreading Combinational critical cells 41

Iterative Cell Spreading Searching in four directions 42

Iterative Cell Spreading Move the cell to the local optimum position 43

Register Swap Assignment problem 6 F Hungarian algorithm 7 G 5 1 E A 4 LCB 2 D LCB B 3 C Local Clock Network 8 H 1 A 2 B . 3 C . 4 D . 5 E 6 F 7 G 8 H 44

Register Swap Minimize total cost of assignment 6 F 4->F 7 G 2->G 5 1 E A 1->E 6->A 4 LCB 2 D LCB B 5->D LCB 7->B 3 C 8->C 8 H 3->H 1 A 6 2 B 7 . 3 C 8 . 4 D 5 . 5 E 1 6 F 4 7 G 2 8 H 3 45

Register Swap Assumptions 6 F 4->F Registers are equal 7 G 2->G 5 1 E A 1->E 6->A 4 LCB 2 D LCB B 5->D LCB 7->B 3 C Clock network keeps 8->C 8 H 3->H its timing characteristic 1 A 6 2 B 7 . 3 C 8 . 4 D 5 . 5 E 1 6 F 4 7 G 2 8 H 3 46

Register-to-Register Path Fix Early critical paths composed by two registers LCB 47

Register-to-Register Path Fix Moving endpoint register apart LCB 48

ABU Optimization

ABU Reduction Only for area overflow Bins Non Critical Cells ranked by slack 1 2 4 5 3 50

ABU Reduction Move cells to non critical bins Evaluate incremental local timing 1 2 4 5 3 51

Improvement Flow

Incremental Timing-Driven Placement Flow Initial Placement Early Optimization Skew Optimization Iterative Spreading Register Swap Reg-To-Reg Path Fix Late Optimization Clustered Move Buffer Balancing Cell Balancing Load Optimization ABU Reduction 53

Incremental Timing-Driven Placement Flow ● Quality Score Initial Placement ○ Weighted average for timing improvement Early Optimization Skew Optimization Iterative Spreading Register Swap Reg-To-Reg Path Fix Late Optimization Clustered Move Buffer Balancing Cell Balancing Load Optimization ABU Reduction 54

Incremental Timing-Driven Placement Flow ● Quality Score Initial Placement ○ Weighted average for timing improvement Early Optimization ● After each Step Skew Optimization ○ Steiner Trees update ○ Timing update Iterative Spreading ○ Evaluate Quality Score improvement Register Swap ○ Rollback last solution if QS decreases ■ Iterative Spreading accepts a certainty Reg-To-Reg Path Fix draw back in QS Late Optimization Clustered Move Buffer Balancing Cell Balancing Load Optimization ABU Reduction 55

Incremental Timing-Driven Placement Flow ● Quality Score Initial Placement ○ Weighted average for timing improvement Early Optimization ● After each Step Skew Optimization ○ Steiner Trees update ○ Timing update Iterative Spreading ○ Evaluate Quality Score improvement Register Swap ○ Rollback last solution if QS decreases ■ Iterative Spreading accepts a certainty Reg-To-Reg Path Fix draw back in QS ● After each cell movement Late Optimization ○ Update locally Steiner Trees Clustered Move ○ Update locally timing ○ Evaluate timing cost Buffer Balancing ■ 2Xcentrality + criticality Cell Balancing ○ Reject movement if timing cost increases Load Optimization ○ Legalize cell ABU Reduction 56

Cell Legalization ● Incremental legalization ● Nearest area with enough free space 57

Cell Legalization ● Incremental legalization ● Nearest area with enough free space ● Placing cell in the available position ● Placed cells are not moved 58

Experimental Results

Experimental Setup ● UPlacer tool ● C++-11 ● Incremental Timer ● Incremental Legalizer - Jezz ● Two maximum cell displacement (short and long) ● 2015 ICCAD contest benchmark ○ 8 circuits ● Comparison with 1st Placed team at 2015 ICCAD contest 60

Short Displacement Comparison with 1st Placed team at 2015 ICCAD contest 61

Long Displacement Comparison with 1st Placed team at 2015 ICCAD contest 62 67% of improvement in QS compared with first place at ICCAD 2015 contest

Individual Techniques Gain 63

Conclusion ● Incremental Timing-driven Placement flow ● Local-Cell move techniques ● Optimize early and late timing violations ● Wire load capacitance and resistance ● Outperforms state-of-arts results (ICCAD 15 contest teams) ● Local Timing improvement can achieve a huge minimization in timing violation 64

Drive Strength Aware Cell Movement Techniques for Timing Driven Placement Guilherme Flach, Mateus Fogaça, Jucemar Monteiro, Marcelo Johann and Ricardo Reis Universidade Federal do Rio Grande do Sul (UFRGS) - Brazil jucemar.monteiro@inf.ufrgs.br

Timing Evaluation Metric Quality Score (QS) QS = 10 x ΔTNS late + 2 x ΔTNS early + 5 x ΔWNS late + ΔWNS early 66