Digital HCAL Electronics Status of Electronics Production Gary Drake Argonne National Laboratory CALICE Collaboration Meeting Arlington, TX Mar. 10-12, 2010
RPC DHCAL Collaboration: 36 People, 7 Institutions Argonne National Laboratory Boston University McGill University Carol Adams John Butler François Corriveau Mike Anthony Eric Hazen Daniel Trojand Tim Cundiff Shouxiang Wu Eddie Davis UTA Pat De Lurgio Fermilab Jacob Smith Gary Drake Alan Baumbaugh Jaehoon Yu Kurt Francis Lou Dal Monte Robert Furst Jim Hoff Vic Guarino Scott Holm Bill Haberichter Ray Yarema Andrew Kreps Zeljko Matijas IHEP Beijing José Repond Qingmin Zhang Jim Schlereth Frank Skrzecz University of Iowa (Jacob Smith) Burak Bilki (Daniel Trojand) Ed Norbeck Dave Underwood David Northacker Ken Wood RED = Electronics Contributions Yasar Onel GREEN = Mechanical Contributions Lei Xia BLUE = Students Allen Zhao BLACK = Physicists DHCAL Electronics – Status & Plans 2 G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington
Brief Overview of System DHCAL Electronics – Status & Plans 3 G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington
General Electronics System Specifications Front-end instrumentation to use 64-channel custom ASIC – 1 cm 2 pads, 1 meter 2 planes, 40 planes, 400,000 channels Front-end channel consists of amplifier/shaper/discriminator Single programmable threshold 1 bit dynamic range – Threshold DAC has 8-bit range – Common threshold for all 64 channels per ASIC 2 gain ranges – High gain for GEMs (10 fC - ~200 fC signals) – Low gain for RPCs (100 fC - ~10 pC signals) 100 nSec time resolution Timestamp each hit – 1 second dynamic range 24 bits @ 100 nSec – Synchronize timestamps over system Data from FE consists of hit pattern in ASIC + timestamp – 24 bit timestamp + 64 hit bits = 88 bits (+ address, error bits, etc.) – Readout format: 16 bytes per ASIC DHCAL Electronics – Status & Plans 4 G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington
General Electronics System Specifications (Continued) Capability for Self Triggering Noise, Cosmic rays, Data errors Capability for External Triggering Primary method for beam events – 20-stage pipeline 2 Sec latency @ 100 nSec Capability of FE to source prompt Trigger Bit (simple OR of all disc.) Capability to store up to 7 triggers in ASIC output buffer (FIFO) Design for 100 Hz (Ext. Trig) nominal rate Deadtimeless Readout (within rate limitations) Zero-suppression implemented in front-end On-board charge injection with programmable DAC Design for 10% occupancy Concatenate data in front-ends Use serial communication protocols Slow controls separate from data output stream Compatibility with CALICE DAQ DHCAL Electronics – Status & Plans 5 G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington
Detector Configuration Chamber Construction with Electronics: ASIC Front-End PCB Communication Link GND Conductive Epoxy Glue Pad Board Signal pads Mylar 8.6 mm Resistive paint 1.1mm glass 1.2mm gas gap HV Fishing line spacers 1.1mm glass Resistive paint Mylar Aluminum foil (Not to Scale) Grounding is important… DHCAL Electronics – Status & Plans 6 G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington
System Block Diagram Front End - On Detector Back End Front End Data CALICE DAQ Motherboard Concentrator Detector Pads Inputs from DCAL 64 CH Control Custom VME 4-PR ASIC Driver/Receiver Interface Driver/Receiver CAT5 Data Decoder 24 Control, VME Data Collector Timing Timing, Crate Detector Pads Inputs from DCAL Trig Out 64 CH Trigger Custom Data Inputs ASIC Timing & Backplane Trig Input Trig Out Data Both on Same PCB Collector VME Timing & Trig Module Ext. Clock SLAVE (Optional) To VME Other Timing SLAVES & Trig Ext. Trigger Module MASTER DHCAL Electronics – Status & Plans 7 G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington
System Physical Implementation Plane Construction Gas Outlet – A plane consists of 3 independent chambers – See Lei Xia’s talk Friday Chambers – 3 per plane Gas HV Inlet Square Meter Plane (3) 32 cm X 96 cm chambers DHCAL Electronics – Status & Plans 8 G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington
System Physical Implementation (Cont.) Power Serial Communication Link Data - 1 per Front-End Bd Concentrator Chambers – 3 per plane Front End Board with DCAL Chips & Integrated DCON Front End Board Square Meter Plane – (24) 64-Ch Chips / Bd (2) 32 cm X 48 cm Front End Boards per Chamber – 1536 Channels / Bd DHCAL Electronics – Status & Plans 9 G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington
System Physical Implementation (Cont.) Pad Boards – Glued to Front End Board using Conductive Epoxy – Gluing done by robot, after FEB assembly and check out – More in Lei Xia’s Talk on Friday Front End Board - Top Pad Board - Bottom DHCAL Electronics – Status & Plans 10 G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington
System Physical Implementation (Cont.) Data Collectors – Need 10 Data VME Interface Optional Power GPS IN Ext. Trig In Data Concentrator MASTER TTM Chambers – 3 per plane To PC Timing Module Front End Board - Double Width with DCAL Chips 6U VME Crate - - 16 Outputs & Integrated DCON SLAVE TTM Data Collectors – Need 10 VME Interface To PC Serial Communication Link 6U VME Crate - 1 per Front-End Bd Square Meter Plane DHCAL Electronics – Status & Plans 11 G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington
System Physical Implementation (Cont.) Square meter plane mounted on cassette using prototype Front End Boards Plane #1 !!! DHCAL Electronics – Status & Plans 12 G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington
Some Numbers Planes 38 planes in m 3 – Detector Granularity 1 cm 2 pads – – 10,000 pads/plane – 380,000 ch total Front End Boards – 6 per plane – 228 total (+ spares) Chips – 64 ch/chip Chip Rates (@ 1 TS/trig) DCON Output Rates – 24 chips/FEB – 1 bit/100 nSec out of chips – 16 bytes/TSlice/chip – 121 bits/TSlice – 25 nSec/nibble – 5472 chips total • 64 hit bits 8 bytes 12.8 uSec/TSlice/chip – Data Collectors • 24 bits timestamp 3 bytes – 78 K Tslices/sec max rate – 12 FEB/Data Coll. • 3 ctrl bit/byte – Zero Suppression helps – 20 Data Coll. total – 12.1 uSec/TS/Chip – Example: VME Crates – 24 chips operate in parallel • 4 chips hit/event avg 82.6 KHz max average – – 2 crates total (1 per side) • Max event rate: 19KHz event rate – WC: 78 K / 24 = 3.2 KHz – Use Zero Suppression… DHCAL Electronics – Status & Plans 13 G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington
Power Distribution System Cubic meter detector power requirements: Power Numbers – 3A / FEB @ 5V – 100 mA/ASIC @ 2.5V – 40 planes * 6 FEBs/plane * 3.0 amps/FEB = 720 amps at 5V – 3.9 mW/ch Solution: – 3A/FEB @ 5V (ASICs run at 2.5V) – 5 Wiener PL508 chassis – 15W/FEB – Each PL508 has six independent 5V at 30 amp supplies – 90W/plane – 5 PL508 * 6 PS/PL508 * 30 amps/PS = 900 amps total ampacity – 3.6 KW/cubic meter – Operate at ~80% of capacity – 1 Wiener supply powers 8 Front End Boards Not designed for Low Power… DHCAL Electronics – Status & Plans 14 G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington
Power Distribution System (Cont.) Need Power Dist. Box to distribute voltages to Front End Boards Rack Configuration – Power supplies will fit into one rack Power Distribution – Custom distribution boxes, with fuses, safe wiring, etc. Distribution Box Wiener PL508 30A To 1 Front-End Bd 3A Nominal 30A 30A 30A 30A 30A DHCAL Electronics – Status & Plans 15 G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington
Production Quantities Item Needed for Possible Spares Teststands Total Detector Tail Catcher DCAL Chips 5472 1008 2164 0* 8644 Front End Bds 228 42 10 0* 280 Data Collectors 20 4 3 1 28 VME Crates 2 0 1 2 5 VME Processors 2 0 1 1 4 Timing Module 3 0 2 3 8 Wiener Power 5 2 1 0 8 Supplies Power Dist. 5 2 1 0 8 Boxes * Use Prototypes DHCAL Electronics – Status & Plans 16 G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington
Status of System Components to Date DHCAL Electronics – Status & Plans 17 G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington
Status of DCAL3 Production Chip Fabrication: – 11 wafers, 10,300 chips, fabricated, packaged, in-hand Chip Testing – All chips tested using robot at Fermilab – Results: • 8644 good parts 84% yield Average • 1 bad wafer 25% yield Did not use Complete DCAL3 Layout Robotic Chip Tester Chip Storage (~1/2 total) DHCAL Electronics – Status & Plans 18 G. Drake – Mar. 11, 2010 – CALICE Meeting – Arlington
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