CSE 140 Lecture 17 System Design II CK Cheng CSE Dept. UC San Diego 1
Design Process • Describe system in programs • Data subsystem – List data operations – Map operations to functional blocks – Add interconnect for data transport – Input control signals and output conditions • Control Subsystem – Derive the sequence according to the hardware program – Create the sequential machine – Input conditions and output control signals 2
Example: Multiplication Input X, Y Output Z Arithmetic Variable M, i Z=X × Y • M=0 • M=0 • For i=n-1 to 0 – If Y n-1 =1, M=M+X • For i=n-1 to 0 – Shift Y left by one bit – If Y i =1, M=M+X × 2 i – If i != 0, shift M left by one • Z=M bit • Z=M 3
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Implementation: Example Multiply(X, Y, Z, start, done) { Input X[15:0], Y[15:0] type bit-vector, start type Boolean; Local-Object A[15:0], B[15:0] ,M[31:0], i[4:0] type bit- vector; Output Z[31:0] type bit-vector, done type Boolean; S0: If start’ goto S0 || done 1; S1: A X || B Y || i 0 || M 0 || done 0; S2: If B 15 = 0 goto S4 || i i+1; S3: M M+A; S4: if i>= 16, goto S6 S5: M Shift(M,L,1) || B Shift(B,L,1) || goto S2; S6: Z: M || done 1|| goto S0; } 5
Step 0: Syntax Multiply(X, Y, Z, start, done) { Input X[15:0], Y[15:0] type bit-vector, start type boolean; Local-Object A[15:0], B[15:0] ,M[31:0], i[4:0] type bit- vector; Output Z[31:0] type bit-vector, done type boolean; S0: If start’ goto S0 || done 1; S1: A X || B Y || i 0 || M 0 || done 0; S2: If B 15 = 0 goto S4 || i i+1; S3: M M+A; S4: if i>= 16, goto S6 S5: M Shift(M,L,1) || B Shift(B,L,1) || goto S2; S6: Z: M || done 1|| goto S0; } 6
Step 1: Identify Input and Output of data and control subsystems Multiply(X, Y, Z, start, done) Z=XY { Input: X[15:0], Y[15:0] type bit- vector, start type boolean; Local-Object : A[15:0], B[15:0] 16 32 X ,M[31:0], i[4:0] type bit-vector; Data Z 16 Output Z[31:0] type bit-vector, Y Subsystem done type boolean; ? B 15 ,i 4 S0: If start’ goto S0 || done 1; S1: A X || B Y || i 0 || M 0 || start Control done 0; done Subsystem S2: If B 15 = 0 goto S4 || i i+1; S3: M M+A; S4: if i>= 16, goto S6 S5: M Shift(M,L,1) || B Shift(B,L,1) || goto S2; S6: Z: M || done 1|| goto S0; 7 }
Step 2: Identify Condition Bits to Control Subsystem Multiply(X, Y, Z, start, done) { Input: X[15:0], Y[15:0] type bit-vector, start type boolean; Local-Object : A[15:0], B[15:0] ,M[31:0], 16 i[4:0] type bit-vector; 32 X Data 16 Output Z[31:0] type bit-vector, done type Z Y Subsystem boolean; S0: If start’ goto S0 || done 1; B 15, , i 4 ? S1:A X || B Y || i 0 || M 0 || done 0; S2: If B 15 = 0 goto S4 || i i+1; Control start S3: M M+A; Subsystem done S4: if i>= 16, goto S6 S5: M Shift(M,L,1) || B Shift(B,L,1) || goto S2; S6: Z: M || done 1|| goto S0; } 8
Step 3: Identify Data Subsystem Operations Multiply(X, Y, Z, start, done) Z=XY { Input: X[15:0], Y[15:0] type bit-vector, start type boolean; 16 Local-Object : A[15:0], B[15:0] ,M[31:0], 32 X Data i[4:0] type bit-vector; 16 Z Y Subsystem Output Z[31:0] type bit-vector, done type boolean; B 15 ,i 4 ? S0: If start’ goto S0 || done 1; S1: A X || B Y || i 0 || M 0 || done 0; S2: If B 15 = 0 goto S4 || i i+1; Control start S3: M M+A; Subsystem done S4: if i>= 16, goto S6 S5: M Shift(M,L,1) || B Shift(B,L,1) || goto S2; S6: Z: M || done 1|| goto S0; } 9
Step 4: Map Data Operations to Implementable functions Multiply(X, Y, Z, start, done) { Input: X[15:0], Y[15:0] type bit-vector, operation start type boolean; A Load (X) A X Local-Object : A[15:0], B[15:0] ,M[31:0], B Load (Y) B Y i[4:0] type bit-vector; M Clear(M) M 0 Output Z[31:0] type bit-vector, i Clear(i) i 0 done type boolean; i INC(i) i i+ 1 S0: If start’ goto S0 || done 1; M Add(M,A) M M+A S1: A X || B Y || i 0 || M 0 || done 0; M SHL(M) M Shift(M,L,1) S2: If B 15 = 0 goto S4 || i i+1; B SHL(B) B Shift(B,L,1) S3: M M+A; Z: M Wires S4: if i>= 16, goto S6 S5: M Shift(M,L,1) || B Shift(B,L,1) || goto S2; S6: Z: M || done 1|| goto S0; } 10
Step 5: Implement the Data Subsystem from Standard Modules D Registers: If C then R D LD C R operation A Load (X) B Load (Y) M Clear(M) i Clear(i) i INC(i) M Add(M,A) M SHL(M) B SHL(B) 11
Storage Component: Registers with control signals D Registers: If C then R D LD C R Register A operation A Load (X) D Register M R X B Load (Y) A 16 LD M Clear(M) D R M i Clear(i) 32 CLR i INC(i) Register B M Add(M,A) 16 D R Y M SHL(M) LD B SHL(B) B[15] 12
Data Subsystem operation A Load (X) Register A B Load (Y) D R X M Clear(M) A 16 LD Register M i Clear(i) i INC(i) D R M M Add(M,A) 32 CLR M SHL(M) B SHL(B) Register B 16 R D Y B LD 13
Function Modules: Adder, Shifter operation A Load (X) B Load (Y) Selector A Register A M Clear(M) Register M Adder i Clear(i) S D R 0 B X R D A i INC(i) 1 M 16 LD 32 CLR LD M Add(M,A) C 0 << M SHL(M) C 3 C 1 C 4 SHL B SHL(B) Selector Register B 16 Y Registers B and M have 0 B B[15] D R multiple sources. 1 << LD SHL C 5 C 2 14
Function Modules: Adder, Shifter, Counter operation A Load (X) B Load (Y) Selector A Register A Register M M Clear(M) Adder i Clear(i) S D R 0 B X R D A i INC(i) 1 M 16 LD 32 CLR LD M Add(M,A) C 0 << M SHL(M) C 3 C 1 C 4 SHL B SHL(B) Selector Register B 16 Y Counter i 0 B B[15] D R D R 1 << LD SHL CLR Inc i[4] C 2 C 5 C 6 C 7 15
Step 6: Map Control Signals to Operations control operation C 0 =1 A Load (X) Selector Register A A C 2 =0 and C 5 =1 B Load (Y) Register M Adder C 3 =1 M Clear(M) S R D C 6 =1 0 i Clear(i) B X R D A M 1 C 7 =1 16 i INC(i) LD 32 LD CLR C 1 =0 and C 4 =1 M Add(M,A) C 0 << C 1 =1 and C 4 =1 M SHL(M) C 3 C 1 C 4 SHL C 2 =1 and C 5 =1 B SHL(B) Selector Register B 16 Y Counter i 0 B B[15] D R D R 1 << LD SHL CLR Inc i[4] C 2 C 5 C 6 C 7 16
Step 7: Identify Control Path Components Z=XY Multiply(X, Y, Z, start, done) { Input: X[15:0], Y[15:0] type bit-vector, start type boolean; Local-Object : A[15:0], B[15:0] ,M[31:0], 16 32 X Data i[4:0] type bit-vector; 16 Output Z[31:0] type bit-vector, Z Y Subsystem done type boolean; S0: If start’ goto S0 || done 1; C 0:7 B[15], i[4] S1: A X || B Y || i 0 || M 0 || done 0; S2: If B 15 = 0 goto S4 || i i+1; Control S3: M M+A; start done Subsystem S4: if i>= 16, goto S6 S5: M Shift(M,L,1) || B Shift(B,L,1) || goto S2; S6: Z: M || done 1|| goto S0; i[4] C 0-7 Control } B[15] Unit done start 17
16 32 X Data 16 Z Y Subsystem B[15], i[4] C 0:7 Control start done Subsystem 18
operation control Multiply(X, Y, Z, start, done) { A Load (X) C 0 =1 S0: If start’ goto S0 || done 1; B Load (Y) C 2 =0 and C 5 =1 S1: A X || B Y || i 0 || M 0 || done 0; M Clear(M) C 3 =1 S2: If B 15 = 0 goto S4 || i i+1; i Clear(i) C 6 =1 S3: M M+A; i INC(i) C 7 =1 S4: if i>= 16, goto S6 M Add(M,A) C 1 =0 and C 4 =1 S5: M Shift(M,L,1) || B Shift(B,L,1) || goto S2; M SHL(M) C 1 =1 and C 4 =1 S6: Z: M || done 1|| goto S0;} B SHL(B) C 2 =1 and C 5 =1 C2 C0 C1 C3 C4 C5 C6 C7 done Feed B Load A Feed M Clr M Load M Load B Clr i Inc i S0 0 0 0 0 0 0 1 S1 1 1 0 1 1 0 0 S2 0 0 0 0 0 1 0 S3 0 0 1 0 0 0 0 S4 0 0 0 0 0 0 0 S5 0 0 1 1 0 0 0 S6 0 0 0 0 0 0 1 19
Multiply(X, Y, Z, start, done) { operation control S0: If start’ goto S0 || done 1; A Load (X) C 0 =1 S1: A X || B Y || i 0 || M 0 || done 0; B Load (Y) C 2 =0 and C 5 =1 S2: If B 15 = 0 goto S4 || i i+1; M Clear(M) C 3 =1 S3: M M+A; i Clear(i) C 6 =1 S4: if i>= 16, goto S6 i INC(i) C 7 =1 S5: M Shift(M,L,1) || B Shift(B,L,1) || goto S2; M Add(M,A) C 1 =0 and C 4 =1 S6: Z: M || done 1|| goto S0;} M SHL(M) C 1 =1 and C 4 =1 B SHL(B) C 2 =1 and C 5 =1 C0 C1 Feed M C2 C3 C4 C5 C6 C7 done Load A Clr M Load M Load B Feed B Clr i Inc i S0 0 X X 0 0 0 0 0 1 S1 1 X 0 1 0 1 1 0 0 S2 0 X X 0 0 0 0 1 0 S3 0 0 X 0 1 0 0 0 0 S4 0 X X 0 0 0 0 0 0 S5 0 1 1 0 1 1 0 0 0 S6 0 X X 0 0 0 0 0 1 20
Design of the Control Subsystem Multiply(X, Y, Z, start, done) { i[4] C 0-7 S0: If start’ goto S0 || done 1; Control B[15] Subsystem S1: A X || B Y || i 0 || M 0 || done start done 0; S2: If B 15 = 0 goto S4 || i i+1; S3: M M+A; S4: if i>= 16, goto S6 S5: M Shift(M,L,1) || B Shift(B,L,1) || goto S2; S6: Z: M || done 1|| goto S0 } 21
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