Analysis of TDMA Crossbar Real-Time Switch Design for AFDX Networks - PowerPoint PPT Presentation

Analysis of TDMA Crossbar Real-Time Switch Design for AFDX Networks Lei Rao ‡ † *, Qixin Wang ‡ , Xue Liu † , Yufei Wang ‡ ‡ Department of Computing, The Hong Kong Polytechnic University, China † School of Computer Science, McGill University, Canada * Presenter, now working at General Motors Research Lab, United States. Contact information: lei.rao@gm.com March 29, 2012

Content Background Problem Statement and Analysis Resource Planning Problem and Approximation Algorithm Related Work Conclusion

Background: Avionics Full DupleX (AFDX) Switched Ethernet AFDX is a data network for safety-critical applications that utilizes dedicated bandwidth while providing deterministic Quality of Service (QoS). – from wikipedia  10/100Mbit switched Ethernet  Based upon IEEE 802.3 and ARINC 664  Bridges the gap on reliability of guaranteed bandwidth in ARINC 664  Adopted by Airbus A380, Boeing 787 Dreamliner etc AFDX Network

AFDX: Properties • Properties in AFDX:  Redundancy for reliable transmission  Virtual links with traffic shaping for end- systems’ communication • Elements in an AFDX network:  AFDX End-system  AFDX Switch  AFDX Links

AFDX: Virtual Links and Switches  Each VL conducts one unicast flow from a source-end to a destination-end (e.g. E1 to E5) ;  Along the VL’s route, before entering each AFDX node, the VL flow must behave as if policed by a token bucket;  With the per hop token bucket policing and proper switch architecture design, we can guarantee end-to-end real-time for each VL.

Problem Statement: AFDX Switch Architecture Design • AFDX standard leaves the switch architecture design open – Challenge • Vendors want to reuse the legacy switch architecture instead of a complete re-design – Design goals • Build AFDX networks using a popular real-time switch, which we call TDMA crossbar real-time switch • Compliance with many mainstream non-real-time switch architectures

AFDX Switch Architecture Design • Basic idea & approaches – Prove that TDMA crossbar real-time switched network is AFDX compliant • Traffic pattern & e2e real-time delay bound – Discuss the AFDX network’s resource planning problem • NP-hard – Re-model and approximate the NP-hard problem

Background: TDMA Crossbar Real-Time Switch architecture • Features – Packets are buffered at the inputs • All packets are fragmented into same-size units called cells • Each input carries out per-flow queueing – Outputs fetch/ forward cells synchronously and periodically • The period is called a cell-time • Each output runs a static TDMA schedule of M cell-time • Advantages – Simple design/schedulability analysis – High switch utilization – Complie/simplifie with mainstream Internet switch architecture

Case Study: TDMA Crossbar Real-Time Switch Scheduling We consider messages in terms of a cell-time e.g 1 cell = 1 bit; 1 cell-time =1 ns TDMA scheduling frame of M cell-time, e.g., M = 5 Fit all real-time flows’ periods into frame, e.g., (11, 3)  (5, 2), i.e., (10, 4) (11,3): sending a message of 3 cells every 11 cell-time VM-task (5,2): the real-time task is served 2 cell-time units during each clock period of 5 cell times Demand Cell time: 1 2 3 4 5 a cell to send to O 1 I 1: a cell to send to O 2 I 2: a cell to send to O 3 I 3: a cell to send to O 4 I 4:

Case Study: TDMA Crossbar Real-Time Switch Scheduling Schedule Theorem 1 (Schedulability): If Cell time: 1 2 3 4 5 demand matrix’ every color I 1:  ≤ M cell, then have config. I 2: time scheduler with O ( N 4 ) time cost [TII10]. I 3: I 4: Demand Cell time: 1 2 3 4 5 Scheduling a cell to send to O 1 Algorithm I 1: a cell to send to O 2 I 2: a cell to send to O 3 I 3: a cell to send to O 4 I 4:

Analysis: AFDX Compliance L f : flow f’s in-network maximum packet length H f : total number of hops for a flow M: frame size P f : flow f’s in-network period C f : per-frame allocated slots AFDX compliance  Along the VL’s route, before entering each AFDX switch, the VL flow must behave as if policed by a token bucket;  With the per hop token bucket policing and proper switch architecture design, we can guarantee end-to-end real-time for each VL

Analysis: AFDX Compliance • Theorem 2 (AFDX Compliance) – Per flow analysis with network calculus – Giving end to end delay (1) (Hf-1) (0) s f s f s f (1) (Hf-1) (Hf) (0) a f a f a f a f .. src V 0 V 1 V Hf-1 V Hf end src end : source (des end) a : arrival curve for each flow at a switch s : service curve for each flow at a switch v : TDMA crossbar real-time switch des end : destination ө f : flow f’s required cell time u f : flow f’s utilization

Resource Planning Problem P(G(V,E),F) : TDMA crossbar real-time switch AFDX network resource planning problem • AFDX network G(V,E) , where V is the set of all switches and E is the set of links between the switches • F is the set of flow in the AFDX network Objective network utility maximization Constraints switch schedulability Constraints end-to-end delay guarantee

Resource Planning Problem: NP-Hard Objective network utility maximization Constraints switch schedulability Constraints end-to-end delay guarantee

Analysis: Why NP-Hard • Knapsack problem has been known as NP-Hard • An instance of knapsack problem ҡ ( Ξ , size, value, Ө s , Ө v ) can be reduced to an instance of TDMA crossbar real-time switched AFDX network resource planning problem: – Construct an AFDX network of three nodes: one source-end, connected by one TDMA crossbar switch to one destination end. – becomes equivalent to asking ‘is the constructed resource planning problem results in a maximum ≥ Ө v ’

Approximation Algorithm To address the challenge that resource planning problem P(G(V,E),F) is NP-Hard, we propose a re-modeling approach, upon which, we propose an approximation algorithm for P(G(V,E),F) Definition: A configuration function cfg is a function of F → {0,1,…, ᴧ -1}, where ᴧ denotes all the alternatives of solutions Let U ~ and U * be the total utility corresponding to cfg ~ and the actual optimal cfg * respectively. We have ᴧ : the maximum number of alternatives in the network Π : the set of all ports

Related Work • Analysis of real-time behavior of AFDX networks upon switches [TII 09, ECRTS 06, INFOCOM 11] • Industrial fieldbus designs [IECON 09] • TDMA Crossbar Switch Design [TII 10] • Knapsack problem approximation algorithm

Conclusion • TDMA crossbar real-time switch design for AFDX networks – We proved that TDMA crossbar real-time switched network is AFDX compliant – We proved the corresponding AFDX network’s resource planning problem is NP-Hard – We proposed a re-modeling approach • We proposed an approximation algorithm

Thanks & Questions

Background: Token Bucket  A token bucket flow is defined by ( ρ , σ )  ρ denotes the bucket refilling rate at which tokens(credits) are accumulated  ρ f = L max f (1+J f / BAG f )  σ is the bucket size  σ f = L max / BAG f f  L max : the maximum packet bit length f  BAG f : the bandwidth allocation gap  J f : the maximum admissible jitter

Background: BAG • How to affect QoS? -- Bandwidth • BAG (bandwidth allocation gap) • Primary bandwidth control scheme • Minimum time interval between two successive frames BAG BAG

Background: TDMA Crossbar Real-Time Switch architecture Input Ports I1 I2 I3

Background: TDMA Crossbar Real-Time Switch architecture Output Ports I1 O1 I2 O2 I3 O3

Background: TDMA Crossbar Real-Time Switch architecture Per-Flow-Queueing I1 O1 I2 O2 I3 O3

Background: TDMA Crossbar Real-Time Switch architecture cells I1 O1 I2 O2 I3 O3

Background: TDMA Crossbar Real-Time Switch architecture I1 O1 O2 I2 cell cell cell cell cell cell O3 I3

Background: TDMA Crossbar Real-Time Switch architecture Synchronous periodic cell forwarding Cell-Time I1 O1 I2 O2 I3 O3

Background: TDMA Crossbar Real-Time Switch architecture Matching I1 O1 I2 O2 I3 O3

Background: TDMA Crossbar Real-Time Switch architecture Why Matching? An input/output can only send/receive one cell per cell-time I1 O1 I2 O2 I3 O3

Background: TDMA Crossbar Real-Time Switch architecture Internal Matching: if an input has multiple per-flow-q for the same output, only one is picked every cell-time. I1 O1 I2 O2 I3 O3

Background: TDMA Crossbar Real-Time Switch architecture I1 O1 I2 O2 I3 O3

Background: TDMA Crossbar Real-Time Switch architecture I1 O1 I2 O2 I3 O3

Background: TDMA Crossbar Real-Time Switch architecture I1 O1 I2 O2 I3 O3