CHAPTER II SWITCH NETWORKS AND SWITCH DESIGN R.M. Dansereau; v.1.0 - PowerPoint PPT Presentation

SWITCH DESIGN •CHAPTER II CHAPTER II-1 SWITCH DESIGN CHAPTER II SWITCH NETWORKS AND SWITCH DESIGN R.M. Dansereau; v.1.0

SWITCH NETWORKS SWITCH DESIGN •SWITCH NETWORKS CHAPTER II-2 BASIC IDEAL SWITCH SWITCH DESIGN • Simplest structure in a computing system is a switch IDEAL SWITCH INPUT OUTPUT • Path exists between INPUT and OUTPUT if Switch is CLOSED or ON • Path does not exist between INPUT and OUTPUT if SWITCH is OPEN or OFF R.M. Dansereau; v.1.0

SWITCH NETWORKS SWITCH DESIGN •SWITCH NETWORKS -BASIC SWITCH CHAPTER II-3 SWITCHES IN SERIES SWITCH DESIGN SWITCHES IN SERIES Truth Table INPUT S1 PATH? S2 OFF OFF NO S1 OFF ON NO ON OFF NO ON ON YES S2 • AND configuration OUTPUT R.M. Dansereau; v.1.0

SWITCH NETWORKS SWITCH DESIGN •SWITCH NETWORKS -BASIC SWITCH CHAPTER II-4 -SWITCHES IN SERIES SWITCHES IN PARALLEL SWITCH DESIGN SWITCHES IN PARALLEL Truth Table INPUT S1 PATH? S2 OFF OFF NO OFF ON YES ON OFF YES S1 S2 ON ON YES • OR configuration OUTPUT R.M. Dansereau; v.1.0

SWITCH NETWORKS SWITCH DESIGN •SWITCH NETWORKS -BASIC SWITCH CHAPTER II-5 -SWITCHES IN SERIES INPUT SELECTOR SWITCH DESIGN -SWITCHES IN PARALLEL INPUT 1 Truth Table S1 S1 OUTPUT S2 OFF OFF NONE OUTPUT OFF ON INPUT 2 ON OFF INPUT 1 S2 ON ON UNKNOWN • Crowbarred level where logic level is INPUT 2 indeterminate. Likely avoid this case. R.M. Dansereau; v.1.0

CMOS SWITCH DESIGN •SWITCH NETWORKS -SWITCHES IN SERIES CHAPTER II-6 -SWITCHES IN PARALLEL CMOS SWITCHES SWITCH DESIGN -INPUT SELECTOR • The idea is to use the series and parallel switch configurations to route signals in a desired fashion. • Unfortunately, it is difficult to implement an ideal switch as given. • Complementary Metal Oxide Semiconductor (CMOS) devices give us some interesting components. IDEAL SWITCH nMOS transistor pMOS transistor INPUT DRAIN SOURCE SWITCH GATE GATE OUTPUT SOURCE DRAIN R.M. Dansereau; v.1.0

CMOS SWITCH DESIGN •SWITCH NETWORKS •CMOS CHAPTER II-7 -CMOS SWITCHES TRANSFER CHARACTERISTICS SWITCH DESIGN • nMOS when CLOSED nMOS SWITCH S • Transmits logic level 0 well 0 OPEN S 1 CLOSED • Transmits logic level 1 poorly • pMOS when CLOSED pMOS SWITCH S • Transmits logic level 1 well 0 CLOSED S • Transmits logic level 0 poorly 1 OPEN R.M. Dansereau; v.1.0

CMOS SWITCH DESIGN •SWITCH NETWORKS •CMOS CHAPTER II-8 -CMOS SWITCHES TRANSMISSION GATE (1) SWITCH DESIGN -TRANSFER CHAR. S IDEAL SWITCH INPUT OUTPUT S CMOS TRANSMISSION GATE INPUT OUTPUT (SWITCH) S S nMOS pMOS OUTPUT S 0 OFF OFF Z INPUT OUTPUT 1 ON ON INPUT S R.M. Dansereau; v.1.0

CMOS SWITCH DESIGN •CMOS -CMOS SWITCHES CHAPTER II-9 -TRANSFER CHAR. TRANSMISSION GATE (2) SWITCH DESIGN -TRANSMISSION GATE SPLIT OF CURRENT ACROSS A TRANSMISSION GATE FOR LOGIC-0 AND LOGIC-1 INPUT LOGIC-0 AT INPUT LOGIC-1 AT INPUT S = 0 S = 0 0 0 1 1 S = 1 S = 1 R.M. Dansereau; v.1.0

SWITCH NETWORKS SWITCH DESIGN •CMOS -CMOS SWITCHES CHAPTER II-10 -TRANSFER CHAR. HIGH IMPEDANCE Z (1) SWITCH DESIGN -TRANSMISSION GATE • With switches, we can consider three states for an output: • Logic-0 • Logic-1 • High Impedance Z • Path exists for Logic-0 and Logic-1 when the switch is CLOSED. S 0/1 OUTPUT = 0/1 • High impedance is a state where the switch is OPEN. S 0/1 OUTPUT = Z R.M. Dansereau; v.1.0

SWITCH NETWORKS SWITCH DESIGN •CMOS •SWITCH NETWORKS CHAPTER II-11 -HIGH IMPEDANCE Z HIGH IMPEDANCE Z (2) SWITCH DESIGN • Another way of thinking of switches is as follows • Path exists for Logic-0 and Logic-1 when the switch is CLOSED, meaning that the impedance/resistance is small enough to allow amply flow of current. 1 = CLOSED Ω 10K « SOURCE DRAIN SOURCE DRAIN • High impedance is a state where the switch is OPEN, meaning that the impedance/resistance is very large allowing nearly no current flow. 0 = OPEN Ω 100 M » SOURCE DRAIN SOURCE DRAIN R.M. Dansereau; v.1.0

SWITCH NETWORKS SWITCH DESIGN •CMOS •SWITCH NETWORKS CHAPTER II-12 -HIGH IMPEDANCE Z INVERTER (NOT) SWITCH DESIGN B = A V DD PULL-DOWN PULL-UP A B A B A B A B 0 Z 0 1 0 1 1 0 1 Z 1 0 • This network inverts the binary input value. N R.M. Dansereau; v.1.0 The pull-down network � should be Z "OFF" whenever � the output should be "1". It � should be ON whenever the � output should be "0". Here � "ON" implies "0" The pull-up network should be ON whenever the � output should be "1". It should be "Z" (OFF) � whenever the output should be "0". = Logic "1" = Logic "0"

SWITCH NETWORKS SWITCH DESIGN •CMOS •SWITCH NETWORKS CHAPTER II-13 -HIGH IMPEDANCE Z NAND NETWORK SWITCH DESIGN -INVERTER V DD C = AB PULL-DOWN PULL-UP C A B C A B C A B C A 0 0 Z 0 0 1 0 0 1 0 1 Z 0 1 1 0 1 1 B 1 0 Z 1 0 1 1 0 1 1 1 0 1 1 Z 1 1 0 R.M. Dansereau; v.1.0 The "o" on the gate means � that "Logic 0" voltage turns � the (P-type) transistor "ON". When the gate voltage is "Logic 1", the N-type � transistor turns ON (no inversion).

SWITCH NETWORKS SWITCH DESIGN •SWITCH NETWORKS -HIGH IMPEDANCE Z CHAPTER II-14 -INVERTER NOR NETWORK SWITCH DESIGN -NAND NETWORK C = A + B V DD A PULL-DOWN PULL-UP A B C A B C A B C B 0 0 Z 0 0 1 0 0 1 C 0 1 0 0 1 Z 0 1 0 1 0 0 1 0 Z 1 0 0 1 1 0 1 1 Z 1 1 0 R.M. Dansereau; v.1.0

SWITCH NETWORKS SWITCH DESIGN •SWITCH NETWORKS -INVERTER CHAPTER II-15 -NAND NETWORK AND NETWORK SWITCH DESIGN -NOR NETWORK NAND INVERTER C = AB V DD V DD A B C 0 0 0 C 0 1 0 A 1 0 0 1 1 1 B R.M. Dansereau; v.1.0

SWITCH NETWORKS SWITCH DESIGN •SWITCH NETWORKS -NAND NETWORK CHAPTER II-16 -NOR NETWORK OR NETWORK SWITCH DESIGN -AND NETWORK NOR INVERTER V DD C = A + B V DD A A B C 0 0 0 B 0 1 1 C 1 0 1 1 1 1 R.M. Dansereau; v.1.0

SWITCH NETWORKS SWITCH DESIGN •SWITCH NETWORKS -NOR NETWORK CHAPTER II-17 -AND NETWORK XOR NETWORK SWITCH DESIGN -OR NETWORK V DD C = AB + AB A A A B C B B 0 0 0 C 0 1 1 A A 1 0 1 1 1 0 B B R.M. Dansereau; v.1.0

Complementary _ Circuits B -- _ A-- Boolean Equality AB+A’B’ = (A+B’)(A’+B) Because AA’ = BB’ = 0

SWITCH NETWORKS SWITCH DESIGN •SWITCH NETWORKS -AND NETWORK CHAPTER II-18 -OR NETWORK XNOR NETWORK SWITCH DESIGN -XOR NETWORK V DD C = AB + AB V DD A A A B C 0 0 1 B B 0 1 0 C 1 0 0 A A 1 1 1 B B • Can this be implemented without the extra inverter at the output? Answer: Y es! R.M. Dansereau; v.1.0

SWITCH NETWORKS SWITCH DESIGN •SWITCH NETWORKS -OR NETWORK CHAPTER II-19 -XOR NETWORK PULL-UP/PULL-DOWN SWITCH DESIGN -XNOR NETWORK V DD D = AC + B PULL-UP PULL-DOWN A B C D A B C D A 0 0 0 Z 0 0 0 0 B 0 0 1 Z 0 0 1 0 C 0 1 0 1 0 1 0 Z D 0 1 1 1 0 1 1 Z 1 0 0 1 B 1 0 0 Z 1 0 1 Z 1 0 1 0 1 1 0 1 1 1 0 Z C A 1 1 1 1 1 1 1 Z R.M. Dansereau; v.1.0

SWITCH NETWORKS SWITCH DESIGN •SWITCH NETWORKS -XOR NETWORK CHAPTER II-20 -XNOR NETWORK FUNCTION IMPLEMENTATION SWITCH DESIGN -PULL-UP/PULL-DOWN • Most Boolean functions can be easily implemented using switches. • The basic rules are as follows • Pull-up section of switch network • Use complements for all literals in expression • Use only pMOS devices • Form series network for an AND operation • Form parallel network for an OR operation • Pull-down section of switch network • Use complements for all literals in expression • Use only nMOS devices • Form parallel network for an AND operation • Form series network for an OR operation R.M. Dansereau; v.1.0

SWITCH NETWORKS SWITCH DESIGN •SWITCH NETWORKS -XNOR NETWORK CHAPTER II-21 -PULL-UP/PULL-DOWN EXAMPLE PULL-UP SWITCH DESIGN -FUNC. IMPLEMENTATION • To implement the Boolean function given below, the following pull-up network could be designed. V DD ( ( ) ) F E AD B A C = + + A C A D B E F R.M. Dansereau; v.1.0

SWITCH NETWORKS SWITCH DESIGN •SWITCH NETWORKS -PULL-UP/PULL-DOWN CHAPTER II-22 -FUNC. IMPLEMENTATION EXAMPLE PULL-DOWN SWITCH DESIGN -EXAMPLE PULL-UP • To complete the switch design, the pull-down section for the Boolean function must also be designed. F ( ( ) ) F E AD B A C = + + A B C E A D • Notice how AND and OR become OR and AND circuits, respectively. R.M. Dansereau; v.1.0

SWITCH NETWORKS SWITCH DESIGN •SWITCH NETWORKS -FUNC. IMPLEMENTATION CHAPTER II-23 -EXAMPLE PULL-UP COMPLETED EXAMPLE SWITCH DESIGN -EXAMPLE PULL-DOWN • Putting the pull-up and pull-down pieces together gives the following CMOS switch implementation of the Boolean function. V DD A C A PULL-UP D B E ( ( ) ) F E AD B A C = + + A B C E PULL-DOWN A D R.M. Dansereau; v.1.0