a 1 2v low power 2 4ghz 0 18 m cmos quadrature vco
play

A 1.2V Low-Power 2.4GHz 0.18 m CMOS Quadrature VCO X. Redondo, J. - PowerPoint PPT Presentation

Nov 07, 2023 •102 likes •355 views

DCIS08: A 1.2V Low-Power 2.4GHz QVCO 1/ 26 A 1.2V Low-Power 2.4GHz 0.18 m CMOS Quadrature VCO X. Redondo, J. Pallars, F. Vila , L. Ters and F. Serra-Graells System Integration Department Institut de Microelectrnica de Barcelona

  1. DCIS’08: A 1.2V Low-Power 2.4GHz QVCO 1/ 26 A 1.2V Low-Power 2.4GHz 0.18 μ m CMOS Quadrature VCO X. Redondo, J. Pallarés, F. Vila , L. Terés and F. Serra-Graells System Integration Department Institut de Microelectrònica de Barcelona Centre Nacional de Microelectrònica - CSIC Spain November 2008 F . Vila et al. Centro Nacional de Microelectrónica

  2. DCIS’08: A 1.2V Low-Power 2.4GHz QVCO Intro VCO Quad. Biasing Capac. Bench Layout Res. Con. 2/ 26 1 Introduction 2 VCO Topology 3 Quadrature Generation 4 Bias Control 5 Capacitive Bench 6 Physical Design 7 Experimental Results 8 Conclusions F . Vila et al. Centro Nacional de Microelectrónica

  3. DCIS’08: A 1.2V Low-Power 2.4GHz QVCO Intro VCO Quad. Biasing Capac. Bench Layout Res. Con. 3/ 26 1 Introduction 2 VCO Topology 3 Quadrature Generation 4 Bias Control 5 Capacitive Bench 6 Physical Design 7 Experimental Results 8 Conclusions F . Vila et al. Centro Nacional de Microelectrónica

  4. DCIS’08: A 1.2V Low-Power 2.4GHz QVCO Intro VCO Quad. Biasing Capac. Bench Layout Res. Con. 4/ 26 Scenario � Very Low-Power Superheterodyne TX/RX � PLL with Sigma-Delta Modulation � QVCO specs: � Frequency BandWidth: 2.40-2.48GHz � Phase noise at 1Mhz: -72dBc/Hz � Phase noise at 2Mhz: -95dBc/Hz � Phase noise at 3Mhz: -105dBc/Hz � Quadrature 90º � Low-Gain < 30MHz/V � Very Low-Power < 1mW at 1.2V Power Supply � Technology: 0.18 μ m 1poly 6 metal 1.8V F . Vila et al. Centro Nacional de Microelectrónica

  5. DCIS’08: A 1.2V Low-Power 2.4GHz QVCO Intro VCO Quad. Biasing Capac. Bench Layout Res. Con. 5/ 26 1 Introduction 2 VCO Topology 3 Quadrature Generation 4 Bias Control 5 Capacitive Bench 6 Physical Design 7 Experimental Results 8 Conclusions F . Vila et al. Centro Nacional de Microelectrónica

  6. DCIS’08: A 1.2V Low-Power 2.4GHz QVCO Intro VCO Quad. Biasing Capac. Bench Layout Res. Con. 6/ 26 � Relaxation Oscillator � Ring Oscillator � LC Oscillator Avantatges: Low phase noise One transistor Oscillators High frequency resonators High spectral purity Drawbacks: Low Q factor F . Vila et al. Centro Nacional de Microelectrónica

  7. DCIS’08: A 1.2V Low-Power 2.4GHz QVCO Intro VCO Quad. Biasing Capac. Bench Layout Res. Con. 7/ 26 1 Introduction 2 VCO Topology 3 Quadrature Generation 4 Bias Control 5 Capacitive Bench 6 Physical Design 7 Experimental Results 8 Conclusions F . Vila et al. Centro Nacional de Microelectrónica

  8. DCIS’08: A 1.2V Low-Power 2.4GHz QVCO Intro VCO Quad. Biasing Capac. Bench Layout Res. Con. 8/ 26 Active quadrature � Simulation Results Output Voltage = 550 mVpp Stabilization Time = 90 ns Quadrature Error = 0.2º Phase noise (3MHz) = -120dBc/Hz Harmonic difference = 50 dB Mismatch immunity ↑ F . Vila et al. Centro Nacional de Microelectrónica

  9. DCIS’08: A 1.2V Low-Power 2.4GHz QVCO Intro VCO Quad. Biasing Capac. Bench Layout Res. Con. 9/ 26 1 Introduction 2 VCO Topology 3 Quadrature Generation 4 Bias Control 5 Capacitive Bench 6 Physical Design 7 Experimental Results 8 Conclusions F . Vila et al. Centro Nacional de Microelectrónica

  10. DCIS’08: A 1.2V Low-Power 2.4GHz QVCO Intro VCO Quad. Biasing Capac. Bench Layout Res. Con. 10/ 26 � Double current source � Polarization control using reference follower � Simulation Results � Modified follower F . Vila et al. Centro Nacional de Microelectrónica

  11. DCIS’08: A 1.2V Low-Power 2.4GHz QVCO Intro VCO Quad. Biasing Capac. Bench Layout Res. Con. 11/ 26 1 Introduction 2 VCO Topology 3 Quadrature Generation 4 Bias Control 5 Capacitive Bench 6 Physical Design 7 Experimental Results 8 Conclusions F . Vila et al. Centro Nacional de Microelectrónica

  12. DCIS’08: A 1.2V Low-Power 2.4GHz QVCO Intro VCO Quad. Biasing Capac. Bench Layout Res. Con. 12/ 26 � Switch plus Transistor � Transistor’s operation region � MIM plus Switch CMIM ↑↑ F . Vila et al. Centro Nacional de Microelectrónica

  13. DCIS’08: A 1.2V Low-Power 2.4GHz QVCO Intro VCO Quad. Biasing Capac. Bench Layout Res. Con. 13/ 26 1 Introduction 2 VCO Topology 3 Quadrature Generation 4 Bias Control 5 Capacitive Bench 6 Physical Design 7 Experimental Results 8 Conclusions F . Vila et al. Centro Nacional de Microelectrónica

  14. DCIS’08: A 1.2V Low-Power 2.4GHz QVCO Intro VCO Quad. Biasing Capac. Bench Layout Res. Con. 14/ 26 Full-Custom Layout Design � Reference QVCO � QVCO2 No-bias control � QVCO3 Varactor � QVCO4 N-Well Inductor � QVCO5 Optimized Layout � QVCO6 Standard Cells F . Vila et al. Centro Nacional de Microelectrónica

  15. DCIS’08: A 1.2V Low-Power 2.4GHz QVCO Intro VCO Quad. Biasing Capac. Bench Layout Res. Con. 15/ 26 1 Introduction 2 VCO Topology 3 Quadrature Generation 4 Bias Control 5 Capacitive Bench 6 Physical Design 7 Experimental Results 8 Conclusions F . Vila et al. Centro Nacional de Microelectrónica

  16. DCIS’08: A 1.2V Low-Power 2.4GHz QVCO Intro VCO Quad. Biasing Capac. Bench Layout Res. Con. 16/ 26 Test bench F . Vila et al. Centro Nacional de Microelectrónica

  17. DCIS’08: A 1.2V Low-Power 2.4GHz QVCO Intro VCO Quad. Biasing Capac. Bench Layout Res. Con. 17/ 26 Reference QVCO Results Jitter ~ 2ps � Power: 700 μ A at 1.2V; Freq.: 2.45GHz I/Q Error < 1º PN 3MHz -131 dBc/Hz KVCO 20 MHz/V F . Vila et al. Centro Nacional de Microelectrónica

  18. DCIS’08: A 1.2V Low-Power 2.4GHz QVCO Intro VCO Quad. Biasing Capac. Bench Layout Res. Con. 18/ 26 Output Power � Test bench attenuation: 5.5 dB; Buffers gain : -18 dB. Output Voltage = 500 mVpp F . Vila et al. Centro Nacional de Microelectrónica

  19. DCIS’08: A 1.2V Low-Power 2.4GHz QVCO Intro VCO Quad. Biasing Capac. Bench Layout Res. Con. 19/ 26 Comparison with different versions � Phase noise in QVCO2. � Phase noise in QVCO4. PN 3MHz PN 3MHz -131 dBc/Hz -126 dBc/Hz � Quadrature Error in QVCO5. � Coarse Gain in QVCO3. I/Q Error < 1º KVCO 200 MHz/V F . Vila et al. Centro Nacional de Microelectrónica

  20. DCIS’08: A 1.2V Low-Power 2.4GHz QVCO Intro VCO Quad. Biasing Capac. Bench Layout Res. Con. 20/ 26 Parametric results � Phase noise vs Current. � Phase noise vs Frequency. � Quadrature Error vs Frequency. � Quadrature Error vs Current. F . Vila et al. Centro Nacional de Microelectrónica

  21. DCIS’08: A 1.2V Low-Power 2.4GHz QVCO Intro VCO Quad. Biasing Capac. Bench Layout Res. Con. 21/ 26 State of art comparison � Figure of Merit: Referència V DD [V] I DD [mA] P D [mW] F osc [GHz] Δ f [MHz] L( Δ f) [dBc/Hz] FOM [-] This work 1.20 0.70 0.84 2.50 3.00 -131.68 190.85 1.00 5.00 5.00 6.00 1.00 -120.3 188.87 1.30 16.00 20.80 2.27 3.00 -140.00 184.40 1.80 3.20 5.76 5.50 1.00 -115.00 182.20 2.00 15.00 30.00 1.57 0.60 -133.50 187.08 2.50 8.00 20.00 1.85 3.00 -143.00 185.79 1.25 1.74 2.18 2.01 1.00 -124.00 186.69 1.20 4.40 5.28 6.00 1.00 -117.00 185.34 1.80 9.70 17.46 5.00 1.00 -125.60 187.16 2.50 8.75 21.88 5.20 1.00 -124.00 184.92 0.70 7.40 5.18 2.40 1.00 -124.90 185.36 1.80 6.00 10.80 2.60 0.10 -105.00 182.97 1.80 1.60 2.88 2.40 3.00 -131.50 184.97 1.20 12.25 14.70 2.45 1.00 -120.00 176.11 F . Vila et al. Centro Nacional de Microelectrónica

  22. DCIS’08: A 1.2V Low-Power 2.4GHz QVCO Intro VCO Quad. Biasing Capac. Bench Layout Res. Con. 22/ 26 1 Introduction 2 VCO Topology 3 Quadrature Generation 4 Bias Control 5 Capacitive Bench 6 Physical Design 7 Experimental Results 8 Conclusions F . Vila et al. Centro Nacional de Microelectrónica

  23. DCIS’08: A 1.2V Low-Power 2.4GHz QVCO Intro VCO Quad. Biasing Capac. Bench Layout Res. Con. 23/ 26 Conclusions � Great results on phase noise . � Remarkable results in FOM � Low-current and Low-Power Supply . � Varactor vs capacitors bench. � Importance of mismatch in quadrature generation. � Amplitude noise appears in very-low amplitude output. � Effective bias control improvement. F . Vila et al. Centro Nacional de Microelectrónica

  24. DCIS’08: A 1.2V Low-Power 2.4GHz QVCO 24/ 26 Thank you for your attention!!! F . Vila et al. Centro Nacional de Microelectrónica

Recommend

Adaptive Quadrature for Nystrm Yuchen Su 12/6/17 Quadrature Quadrature Quadrature

Adaptive Quadrature for Nystrm Yuchen Su 12/6/17 Quadrature Quadrature Quadrature

Adaptive Quadrature for Nystrm Yuchen Su 12/6/17 Quadrature Quadrature Quadrature Quadrature Quadrature Quadrature Composite Newton-Cotes Quadrature Composite Gaussian Error Estimation When should we be satisfied with our Quadrature?

792 views • 66 slides
Quadrature Generation Techniques in CMOS Relaxation Oscillators S. Aniruddhan Indian Institute

Quadrature Generation Techniques in CMOS Relaxation Oscillators S. Aniruddhan Indian Institute

Quadrature Generation Techniques in CMOS Relaxation Oscillators S. Aniruddhan Indian Institute of Technology Madras Chennai, India ISCAS 2012 Outline Introduction &amp; Motivation Quadrature Relaxation Oscillators (QRXO)

269 views • 22 slides
CMOS Inverter: Power Dissipation and Sizing CMOS Inverter Power Dissipation Professor Chris H.

CMOS Inverter: Power Dissipation and Sizing CMOS Inverter Power Dissipation Professor Chris H.

CMOS Inverter: Power Dissipation and Sizing CMOS Inverter Power Dissipation Professor Chris H. Kim University of Minnesota Dept. of ECE chriskim@umn.edu Dynamic Power Consumption Where Does Power Go in CMOS? V DD Switching power i L

183 views • 7 slides
Modeling Frequency Response of 65 nm CMOS RF Power Devices CMOS RF P D i i 1 J Usha Gogineni 1

Modeling Frequency Response of 65 nm CMOS RF Power Devices CMOS RF P D i i 1 J Usha Gogineni 1

Modeling Frequency Response of 65 nm CMOS RF Power Devices CMOS RF P D i i 1 J Usha Gogineni 1 , Jesus del Alamo 1 , U h G i d l Al 1 Christopher Putnam 2 , David Greenberg 3 1 Massachusetts Institute of Technology, Cambridge, MA 2 IBM

551 views • 18 slides
CMOS Inverter Two Inverters N Well VDD Share power and ground V DD PMOS is wider Abut cells

CMOS Inverter Two Inverters N Well VDD Share power and ground V DD PMOS is wider Abut cells

The CMOS Inverter: A First Glance V CMOS Inverter DD V in V out Professor Chris H. Kim C L University of Minnesota Dept. of ECE chriskim@umn.edu www.umn.edu/~chriskim/ 2 CMOS Inverter Two Inverters N Well VDD Share power and ground V

240 views • 9 slides
Numerical integration (a.k.a quadrature formulas or quadrature rules) Quadrature rules are used

Numerical integration (a.k.a quadrature formulas or quadrature rules) Quadrature rules are used

Numerical integration (a.k.a quadrature formulas or quadrature rules) Quadrature rules are used to approximate integrals of functions that we are not able to compute exactly. Given g : [ c , d ] R , the most common quadrature rules look like

310 views • 19 slides
4. Numerical Quadrature Where analytical abilities end . . . 4. Numerical Quadrature Numerical

4. Numerical Quadrature Where analytical abilities end . . . 4. Numerical Quadrature Numerical

Preliminary Remarks Simple and Composite Rules Extrapolation Other Approaches Applications of Quadrature 4. Numerical Quadrature Where analytical abilities end . . . 4. Numerical Quadrature Numerical Programming I (for CSE), Hans-Joachim

477 views • 32 slides
4. Numerical Quadrature: Where analytical abilities end . . . 4. Numerical Quadrature: Where

4. Numerical Quadrature: Where analytical abilities end . . . 4. Numerical Quadrature: Where

Preliminary Remarks Simple and Composite Rules Extrapolation Other Approaches Applications of Quadrature 4. Numerical Quadrature: Where analytical abilities end . . . 4. Numerical Quadrature: Where analytical abilities end . . . Numerical

463 views • 32 slides
Quadrature CS3220 - Summer 2008 Jonathan Kaldor What is Quadrature? Numerical evaluation /

Quadrature CS3220 - Summer 2008 Jonathan Kaldor What is Quadrature? Numerical evaluation /

Quadrature CS3220 - Summer 2008 Jonathan Kaldor What is Quadrature? Numerical evaluation / approximation of definite integrals ab f(x) d x What is Quadrature? Recall from calculus that we can compute the integral of a function

710 views • 40 slides
Switch-Less Frequency-Domain Multiplexing of GFET Sensors and Low-Power CMOS Frontend for

Switch-Less Frequency-Domain Multiplexing of GFET Sensors and Low-Power CMOS Frontend for

Switch-Less FDM GFET Sensors LP CMOS Frontend 1024-Ch ECOG Intro FDM ROIC CMOS Chip Conclusions Switch-Less Frequency-Domain Multiplexing of GFET Sensors and Low-Power CMOS Frontend for 1024-Channel ECOG J.Cisneros-Fernndez 1 , M.Dei

517 views • 25 slides
Si CMOS for RF Power Applications J. A. del Alamo MIT Workshop on Advanced Technologies for

Si CMOS for RF Power Applications J. A. del Alamo MIT Workshop on Advanced Technologies for

Si CMOS for RF Power Applications J. A. del Alamo MIT Workshop on Advanced Technologies for Next Generation of RFIC 2005 RFIC Symposium June 12, 2005 Sponsors: DARPA, IBM, SRC RF power applications Power vs. frequency GaAs HEMT 50 InP

699 views • 42 slides
Lesson 2 Quadrature rules 1 Quadrature is the computation of integrals Z b f ( x )

Lesson 2 Quadrature rules 1 Quadrature is the computation of integrals Z b f ( x )

Lesson 2 Quadrature rules 1 Quadrature is the computation of integrals Z b f ( x ) d x a Only in very special cases can integrals be computed exactly, otherwise, we must compute them numerically (i.e., approximately) The

626 views • 50 slides
From numerical quadrature to Pad approximation Claude Brezinski University of Lille - France

From numerical quadrature to Pad approximation Claude Brezinski University of Lille - France

From numerical quadrature to Pad approximation Claude Brezinski University of Lille - France Numerical quadrature Interpolatory quadratures Gaussian quadratures Error estimates Pad approximation of power series

658 views • 35 slides
S E E . F E E L . T O U C H . CMOS type imagers became the default imaging means in consumer

S E E . F E E L . T O U C H . CMOS type imagers became the default imaging means in consumer

CMOS Imaging TODAY Power vs. Resolution PixArt Imaging Technology Call to Action S E E . F E E L . T O U C H . CMOS type imagers became the default imaging means in consumer electronics Dominated by Capture and

269 views • 12 slides
Static Power SCA of Sub-100 nm CMOS ASICs and the Insecurity of Masking Schemes in Low-Noise

Static Power SCA of Sub-100 nm CMOS ASICs and the Insecurity of Masking Schemes in Low-Noise

RUHR-UNIVERSITT BOCHUM Static Power SCA of Sub-100 nm CMOS ASICs and the Insecurity of Masking Schemes in Low-Noise Environments Thorben Moos Ruhr University Bochum, Horst Grtz Institute for IT Security, Germany August 28th, 2019 Section 1

735 views • 56 slides
Fast Bayesian automatic Fast Bayesian automatic adaptive quadrature adaptive quadrature Gh.

Fast Bayesian automatic Fast Bayesian automatic adaptive quadrature adaptive quadrature Gh.

Fast Bayesian automatic Fast Bayesian automatic adaptive quadrature adaptive quadrature Gh. Adam, S. Adam LIT-JINR Dubna, Russia &amp; IFIN-HH Bucharest, Romania Invited Lecture at the RO-LCG 2014 conference, November 3-5, 2014 Outline

551 views • 52 slides
Quadrature Domains in Complex Variables Alan Legg Department of Mathematical Sciences, IPFW

Quadrature Domains in Complex Variables Alan Legg Department of Mathematical Sciences, IPFW

Quadrature Domains in Complex Variables Alan Legg Department of Mathematical Sciences, IPFW October 8, 2016 Quadrature Domains Quadrature domains (QDs) are a special type of domain, traditionally in C , where integrating some class of

896 views • 86 slides
Outline A Brief History CMOS Gate Design Pass Transistors CMOS Latches &amp;

Outline A Brief History CMOS Gate Design Pass Transistors CMOS Latches &amp;

Introduction to CMOS VLSI Design Lecture 1: Circuits &amp; Layout David Harris Harvey Mudd College Spring 2004 Outline A Brief History CMOS Gate Design Pass Transistors CMOS Latches &amp; Flip-Flops Standard Cell Layouts

439 views • 23 slides
1 Low-power Techniques Power-aware Architecture Designs Physical (CMOS) level Utilize low-power

1 Low-power Techniques Power-aware Architecture Designs Physical (CMOS) level Utilize low-power

Importance of Low-power Designs Cost factor for high-end systems High-end systems Lecture 24: Power-efficient Cooling and package cost &gt; 40 W: 1 W $1 Designs Air-cooled techniques: reaching limits Electricity bill

311 views • 4 slides
CMOS technologies in the 1 0 0 nm range CMOS technologies in the 1 0 0 nm range for rad-hard

CMOS technologies in the 1 0 0 nm range CMOS technologies in the 1 0 0 nm range for rad-hard

CMOS technologies in the 1 0 0 nm range CMOS technologies in the 1 0 0 nm range for rad-hard front-end electronics in future collider experim ents p V. Re a,c , L. Gaioni b,c , M. Manghisoni a,c , L Ratti b c V Speziali b c G Traversi a c L.

433 views • 31 slides
Outline Introduction. Paper: System Design for Ultra-Low Power. Bernier, C. Hameau, F.,

Outline Introduction. Paper: System Design for Ultra-Low Power. Bernier, C. Hameau, F.,

Paper presentation Ultra-Portable Devices Outline Introduction. Paper: System Design for Ultra-Low Power. Bernier, C. Hameau, F., et al. An Ultra Low Power SoC for 2.4GHz IEEE802.15.4 wireless communications , Solid-State Circuits

170 views • 6 slides
UMBC A B M A L T F O U M B C I M Y O R T 1 (November 27, 2000 6:34 pm) I E S

UMBC A B M A L T F O U M B C I M Y O R T 1 (November 27, 2000 6:34 pm) I E S

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C CMOS Logic Structures Full complementary static CMOS gates may be undesirable because: The area overhead. Their speed may be too slow. The function may not be feasible as a

772 views • 37 slides
Method of Finite Elements I PhD Candidate - Charilaos Mylonas HIL H33.1 Quadrature and Boundary

Method of Finite Elements I PhD Candidate - Charilaos Mylonas HIL H33.1 Quadrature and Boundary

Method of Finite Elements I PhD Candidate - Charilaos Mylonas HIL H33.1 Quadrature and Boundary Conditions , 26 March, 2018 Institute of Structural Engineering Method of Finite Elements I 1 Quadrature Boundary conditions Outline Quadrature

2.03k views • 27 slides
Integration, Architecture, and Applications of 3D CMOS Memristor Circuits K. T. Tim Cheng

Integration, Architecture, and Applications of 3D CMOS Memristor Circuits K. T. Tim Cheng

Integration, Architecture, and Applications of 3D CMOS Memristor Circuits K. T. Tim Cheng and Dimitri Strukov Univ. of California, Santa Barbara ISPD 2012 1 3D Hybrid CMOS/NANO add-on nanodevices layer top nanowire level CMOS

831 views • 67 slides

More recommend