1 ZELE EE618 LECTURE 20 12 OCT 2018 2 ZELE EE618 L-20 3 - PDF document

1 ZELE EE618 LECTURE 20 12 OCT 2018

2 ZELE EE618 L-20

3 ZELE EE618 L-20

4 ZELE EE618 L-20

5 ZELE EE618 L-20

6 ZELE EE618 L-20

7 ZELE EE618 L-20

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9 ZELE EE618 L-20

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12 ZELE EE618 L-20

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18 ZELE EE618 L-20 Sample of Design Rules provided by the foundry (Below shown rules doesn’t correspond to SCL process) Interconnect layers (Doesn’t correspond to SCL process) MIM Capacitor Top plate connected to M6 M5 acts as botuom plate Dielectric thickness = 56nm

19 ZELE EE618 L-20 Basic Layers in SCL 180nm Difgerent ways of forming Diode Difgerent ways of forming BJT

20 ZELE EE618 L-20 Contacts to regions Top View of NMOS Top View of PMOS Cross sectjonal view of NMOS Cross sectjonal view of PMOS

21 ZELE EE618 L-20 NMOS NMOS Total width = (0.5um) x 2 multjples = 1um Total width = (0.5um) x 2 fjngers = 1um Length= 0.18 um Length= 0.18 um Difgusion resistors

22 ZELE EE618 L-20 Poly resistors

23 ZELE EE618 L-20 MOM Capacitors M k M k-1 Electromigratjon failure htups://web.stanford.edu/class/ee311/NOTES/Interconnect_Al.pdf

24 ZELE EE618 L-20 Layout of the Input Pair of OpAmp using Common-Centroid Layout Comparator Schematjc