cmos analog vlsi design course code ee618 department
play

CMOS Analog VLSI Design Course Code: EE618 Department: Electrical - PowerPoint PPT Presentation

Oct 04, 2023 •117 likes •238 views

CMOS Analog VLSI Design Course Code: EE618 Department: Electrical Engineering Semester: Autumn 2015 Date: July 20, 2015 Instructor: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1 2 What is called an analog element? Why are analog

  1. CMOS Analog VLSI Design Course Code: EE618 Department: Electrical Engineering Semester: Autumn 2015 Date: July 20, 2015 Instructor: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1

  2. 2 What is called an analog element? Why are analog integrated circuits required? IIT-Bombay Lecture 1 M. Shojaei Baghini

  3. 4 Content of the course  Introduction  A review of MOS devices  Biasing concept in analog circuits  Basic single-stage and single-input analog modules  Differential amplifiers  Frequency response of basic analog modules  Feedback theory in analog circuits  Operational amplifiers IIT-Bombay Lecture 1 M. Shojaei Baghini

  4. 5 Content of the course (cont’d)  Reference generators  Noise  Output stages  Comparators  Basic considerations in the layout of analog circuits IIT-Bombay Lecture 1 M. Shojaei Baghini

  5. 6 Course References  Design and Analysis of Integrated Circuits by Paul R. Gray and Meyer, 2009 (main reference 1)  Design of Analog CMOS Integrated Circuits by Behzad Razavi, McGraw Hill, 2001 edition onwards (main reference 2)  CMOS Analog Circuit Design by P. E. Allen et al. , Oxford University Press, 2002 edition onwards.  CMOS circuit design, layout and simulation, by R. J. Baker, IEEE press, 2010.  We may use a paper for the course project IIT-Bombay Lecture 1 M. Shojaei Baghini

  6. 7 Grading  Quiz : (2 quizzes) 10%  Assignments (3): 15% (no late submission!)  Course Project: 15% (no late submission!)  Midsem Exam: 30% (20%)  Final Exam: 30% (40%) • EDA tools: - NGSPICE for circuit simulations - XCircuit for the schematic capture • Technology: 180nm CMOS process (test BSIM3 Version 3.1 model parameters available from MOSIS) BSIM stands for Berkeley Short-channel IGFET Model . IIT-Bombay Lecture 1 M. Shojaei Baghini

  7. 8 Notations for Signals • DC Bias values of the signals • Average value of a signal • Large signal • Small signal IIT-Bombay Lecture 1 M. Shojaei Baghini

  9. 9 Basic Definitions Related to Energy Band Diagram of Materials • Vacuum level: Energy state (energy level) of electrons outside the material (E 0 ) • E c : Lowest energy level corresponding to the conduction band • E v : Highest energy level corresponding to the valence band • Electron affinity: The difference between E 0 and E c IIT-Bombay Lecture 1 M. Shojaei Baghini

  10. 10 MOS Capacitor Structure, Flat-band Condition V FB = ψ g - ψ s (gate and Source: Modern Semiconductor Devices for semiconductor Integrated Circuits by work functions) Chenming C. Hu, 2010 Ex.: V FB = 4.05 -(4.05 + (E c -E f )/q) ≈ -0.7V IIT-Bombay Lecture 1 M. Shojaei Baghini

Recommend

CMOS Analog VLSI Design Course Code: EE618 Department: Electrical Engineering Semester: Autumn

CMOS Analog VLSI Design Course Code: EE618 Department: Electrical Engineering Semester: Autumn

CMOS Analog VLSI Design Course Code: EE618 Department: Electrical Engineering Semester: Autumn 2015 Date: July 21, 2015 Instructor: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1 4 Basic Definitions Related to Energy Band Diagram

294 views • 10 slides
Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 5:

Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 5:

Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 5: January 15, 2018 Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1 2 2 Module 7 Speed and Accuracy Considerations of Analog

322 views • 11 slides
Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 14:

Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 14:

Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 14: February 11, 2020 Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1 2 2 Module 15 Introduction to Quantization (Analog to

341 views • 19 slides
ASIC Physical Design CMOS Processes Smith Text: Chapters 2 & 3 Weste CMOS VLSI

ASIC Physical Design CMOS Processes Smith Text: Chapters 2 & 3 Weste CMOS VLSI

ASIC Physical Design CMOS Processes Smith Text: Chapters 2 & 3 Weste CMOS VLSI Design Global Foundries: BiCMOS_8HP8XP_Training.pdf BiCMOS_8HP_Design_Manual.pdf Physical design process overview CMOS transistor

608 views • 30 slides
UMBC A B M A L T F O U M B C I M Y O R T 1 (November 27, 2000 6:34 pm) I E S

UMBC A B M A L T F O U M B C I M Y O R T 1 (November 27, 2000 6:34 pm) I E S

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C CMOS Logic Structures Full complementary static CMOS gates may be undesirable because: The area overhead. Their speed may be too slow. The function may not be feasible as a

772 views • 37 slides
UMBC A B M A L F T U M B C I O M Y O T R 1 (November 26, 2000 11:15 pm) I E

UMBC A B M A L F T U M B C I O M Y O T R 1 (November 26, 2000 11:15 pm) I E

Principles of VLSI Design Introduction CMPE 413/CMSC 711 Principles of VLSI Design Instructor: Professor Jim Plusquellic Text: Principles of CMOS VLSI Design: A Systems Perspective, by Neil H.E. Weste and Kamran Eshraghian. Supplementary

752 views • 21 slides
Outline A Brief History CMOS Gate Design Pass Transistors CMOS Latches &

Outline A Brief History CMOS Gate Design Pass Transistors CMOS Latches &

Introduction to CMOS VLSI Design Lecture 1: Circuits & Layout David Harris Harvey Mudd College Spring 2004 Outline A Brief History CMOS Gate Design Pass Transistors CMOS Latches & Flip-Flops Standard Cell Layouts

439 views • 23 slides
Mixed-Signal VLSI Design Course Code: EE719/EE410 Department: Electrical Engineering Semester:

Mixed-Signal VLSI Design Course Code: EE719/EE410 Department: Electrical Engineering Semester:

Mixed-Signal VLSI Design Course Code: EE719/EE410 Department: Electrical Engineering Semester: Spring 2011 Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1 2 2 Date: Jan. 14, 2011 Date: Jan. 14, 2011 Analog Filter

610 views • 25 slides
Outline Introduction to CMOS VLSI Design Partitioning Design MIPS Processor Example

Outline Introduction to CMOS VLSI Design Partitioning Design MIPS Processor Example

Outline Introduction to CMOS VLSI Design Partitioning Design MIPS Processor Example Architecture Microarchitecture Lecture 2: Logic Design MIPS Processor Example Circuit Design Physical Design David Harris

490 views • 8 slides
Instruction Encoding Mini-MIPS From Weste/Harris CMOS VLSI Design CS/EE 3710 Based on MIPS

Instruction Encoding Mini-MIPS From Weste/Harris CMOS VLSI Design CS/EE 3710 Based on MIPS

Instruction Encoding Mini-MIPS From Weste/Harris CMOS VLSI Design CS/EE 3710 Based on MIPS Fibonacci C-Code In fact, its based on the multi-cycle MIPS from Patterson and Hennessy Your CS/EE 3810 book... 8-bit version 8-bit

102 views • 9 slides
Digital System Design for Circuit and Electronics Additional material Intro. VLSI: CMOS inverter

Digital System Design for Circuit and Electronics Additional material Intro. VLSI: CMOS inverter

Digital System Design for Circuit and Electronics Additional material Intro. VLSI: CMOS inverter CMOS inverter: black and white representation A counter layout Rules for design rule checking: basic rules Rules for composition Concept of

605 views • 17 slides
Analog/Mixed-Signal Design Challenges in 7-nm CMOS and Beyond A.L.S. Loke, D. Yang, T.T. Wee,

Analog/Mixed-Signal Design Challenges in 7-nm CMOS and Beyond A.L.S. Loke, D. Yang, T.T. Wee,

Session 15 Design Foundations for Advanced Technologies Analog/Mixed-Signal Design Challenges in 7-nm CMOS and Beyond A.L.S. Loke, D. Yang, T.T. Wee, J.L. Holland, P. Isakanian, K. Rim, S. Yang, J.S. Schneider, G. Nallapati, S. Dundigal, H.

558 views • 39 slides
Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 20:

Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 20:

Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 20: February 19, 2018 Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1 2 2 Module 27 Histogram (Code Density Test) for Measuring

598 views • 14 slides
LECTURE 3 1 ZELE EE618 6AUG2019 L-3 2 ZELE EE618 L-3 3 ZELE EE618 L-3 4 ZELE EE618 L-3

LECTURE 3 1 ZELE EE618 6AUG2019 L-3 2 ZELE EE618 L-3 3 ZELE EE618 L-3 4 ZELE EE618 L-3

LECTURE 3 1 ZELE EE618 6AUG2019 L-3 2 ZELE EE618 L-3 3 ZELE EE618 L-3 4 ZELE EE618 L-3 5 ZELE EE618 L-3 6 ZELE EE618 L-3 7 ZELE EE618 EE618 (Zele) Body Effect and Sub-threshold Conduction Body Effect Consider the simplified

444 views • 8 slides
Outline Introduction to CMOS VLSI Introduction Design Delay in a Logic Gate

Outline Introduction to CMOS VLSI Introduction Design Delay in a Logic Gate

Outline Introduction to CMOS VLSI Introduction Design Delay in a Logic Gate Multistage Logic Networks Choosing the Best Number of Stages Lecture 5: Example Logical Effort Summary David Harris Harvey Mudd College

583 views • 8 slides
EE3032 Introduction to VLSI Design Jin-Fu Li Department of Electrical Engineering National

EE3032 Introduction to VLSI Design Jin-Fu Li Department of Electrical Engineering National

EE3032 Introduction to VLSI Design Jin-Fu Li Department of Electrical Engineering National Central University Jhongli, Taiwan A C B C=AxB a b c d z Outline Chapter 1: Introduction to CMOS Circuits Chapter 2: MOS Transistor Theory

2.15k views • 186 slides
Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 14:

Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 14:

Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 14: February 05, 2018 Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1 2 2 Module 18 Sample & Hold Circuit with Buffer

733 views • 12 slides
Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 18:

Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 18:

Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 18: February 13, 2018 Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1 2 2 Module 23 Performance Parameters of Data Converters

344 views • 11 slides
Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 2:

Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 2:

Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 2: January 14, 2019 Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1 2 2 Module 1 Sampling Concept and Bandwidth Limitation

300 views • 29 slides
Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 10:

Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 10:

Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 10: February 03, 2020 Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1 2 2 Module 10 Precision and Speed Considerations Unity

114 views • 9 slides
Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 19:

Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 19:

Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 19: February 15, 2018 Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1 2 2 Module 24 Performance Parameters of Data Converters -

349 views • 15 slides
Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 16:

Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 16:

Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 16: February 08, 2018 Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1 2 2 Module 22 Sampling Approximations s to Z Domain

297 views • 15 slides
Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 4:

Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 4:

Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 4: January 19, 2020 Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1 2 2 Module 3 Coherent Sampling and FFT Simulation

119 views • 11 slides
Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 11:

Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 11:

Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 11: February 04, 2020 Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1 2 2 Module 11 Introduction to the Comparators References

516 views • 17 slides

More recommend