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Energy Limits in A/D Converters August 29, 2012 Boris Murmann murmann@stanford.edu

A/D Converter ca. 1954 P/f s = 500W/50kS/s = 10mJ http://www.analog.com/library/analogDialogue/archives/39-06/data_conversion_handbook.html 8

ADC Landscape in 2004 -6 10 -8 10 P/f snyq [J] -10 10 -12 10 ISSCC & VLSI 1997-2004 20 30 40 50 60 70 80 90 100 110 SNDR [dB] B. Murmann, "ADC Performance Survey 1997-2012," [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html 9

ADC Landscape in 2012 -6 10 -8 10 P/f snyq [J] -10 10 -12 10 ISSCC & VLSI 1997-2004 ISSCC & VLSI 2005-2012 20 30 40 50 60 70 80 90 100 110 SNDR [dB] B. Murmann, "ADC Performance Survey 1997-2012," [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html 10

Observation • ADCs have become substantially “greener” over the years • Questions – How much more improvement can we hope for? – What are the trends and limits for today’s popular architectures? – Can we benefit from further process technology scaling? 11

Outline • Fundamental limit • General trend analysis • Architecture-specific analysis – Flash – Pipeline – SAR – Delta-Sigma • Summary 12

Fundamental Limit Brickwall  1 LPF at f snyq /2  2 C Class-B 2   1 V FS     f 2 2     s SNR P CV f V V V min FS s DD DD FS kT f snyq C OSR P    min E 8kT SNR min f snyq [Hosticka, Proc. IEEE 1985; Vittoz, ISCAS 1990] 13

ADC Landscape in 2004 -6 10 -8 10 Energy [J] -10 10 4x/6dB -12 10 ISSCC & VLSI 1997-2004 -14 10 E min 20 30 40 50 60 70 80 90 100 110 SNDR [dB] 14

ADC Landscape in 2012 -6 10 -8 10 Energy [J] -10 10 4x/6dB -12 10 ISSCC & VLSI 1997-2004 ISSCC & VLSI 2005-2012 -14 10 E min 20 30 40 50 60 70 80 90 100 110 SNDR [dB] 15

Normalized Plot 8 10 ISSCC & VLSI 1997-2004 ISSCC & VLSI 2005-2012 6 10 E ADC /E min 4 10 2 10 ~10,000 ~100  100x in 8 years  3-4x in 8 years 0 10 20 30 40 50 60 70 80 90 100 110 SNDR [dB] 16

Aside: Figure of Merit Considerations • There are (at least) two widely used ADC figures of merit (FOM) used in literature • Walden FOM – Energy increases 2x per bit (ENOB) – Empirical Power  FOM ENOB  2 f snyq • Schreier FOM – Energy increases 4x per bit (DR) – Thermal   BW   FOM DR(dB) 10log   – Ignores distortion   P 17

FOM Lines -6 10 -8 10 Energy [J] -10 10 -12 ISSCC & VLSI 1997-2004 10 ISSCC & VLSI 2005-2012 E min -14 Walden FOM = 10fJ/conv-step 10 Schreier FOM = 170dB 20 30 40 50 60 70 80 90 100 110 SNDR [dB] • Best to use thermal FOM for designs above 60dB 18

Walden FOM vs. Speed 1.E+05 1.E+04 FOM W [fJ/conv-step] 1.E+03 1.E+02 1.E+01 ISSCC 2012 VLSI 2012 ISSCC 1997-2011 VLSI 1997-2011 1.E+00 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 1.E+11 f snyq [Hz] • FOM “corner” around 100…300MHz 19

Schreier FOM vs. Speed 180 ISSCC 2012 VLSI 2012 170 ISSCC 1997-2011 VLSI 1997-2011 160 150 FOM S [dB] 140 130 120 110 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 1.E+11 f snyq [Hz] 20

Energy by Architecture -6 10 -8 10 P/f s [J] -10 10 Flash Pipeline SAR  -12 Other 10 FOM=100fJ/conv-step FOM=10fJ/conv-step 20 30 40 50 60 70 80 90 100 110 SNDR [dB] 21

Flash ADC 2 B -1 D out V in E comp E enc 2 B -1 Decision Levels • High Speed – Limited by single comparator plus encoding logic • High complexity, high input capacitance – Typically use for resolutions up to 6 bits 22

Encoder Assume a Wallace encoder (“ones counter”) • • Uses ~2 B –B full adders, equivalent to ~ 5∙(2 B – B) gates       B E 5 2 B E enc gate 23

Matching-Limited Comparator 2 A C    2 2 VT c A Offset VOS VT WL C ox Required 2 A C   VT ox C C capacitance  c cmin 2 C c C c VOS V Confidence 1   inpp 3 interval VOS B Simple Dynamic Latch 4 2 3dB penalty Assuming C cmin = 5fF  SNR[dB] 3  for wires, clocking, etc. accounts for B 6 “DNL noise”   2   V          2B 2 2 B DD E 144 2 C A C V 2 1   comp ox VT cmin DD 2 V   inpp Matching Energy 24

Typical Process Parameters Process A VT C ox A 2 C ox /kT E gate [fJ] [mV- m m] [fF/ m m 2 ] VT [nm] 250 8 9 139 80 130 4 14 54 10 65 3 17 37 3 32 1.5 43 23 1.5 25

Comparison to State-of-the-Art -6 10 Flash ISSCC & VLSI 1997-2012 E flash65nm -8 10 E comp65nm E min [6] -10 10 [5] P/f snyq [J] [2] [4] [3] [1] -12 10 -14 10 -16 10 15 20 25 30 35 40 SNDR [dB] [1] Van der Plas, ISSCC 2006 [4] Daly, ISSCC 2008 [2] El-Chammas, VLSI 2010 [5] Chen, VLSI 2008 [3] Verbruggen, VLSI 2008 [6] Geelen, ISSCC 2001 (!) 26

Impact of Scaling -6 10 Flash ISSCC & VLSI 1997-2012 E flash250nm E flash130nm -8 10 E flash65nm E flash32nm P/f snyq [J] E min -10 10 -12 10 -14 10 15 20 25 30 35 40 SNDR [dB] 27

Impact of Calibration (1) -6 10 Flash ISSCC & VLSI 1997-2012 E comp65nm -8 10 E comp65nm,cal E min -10 10 P/f snyq [J] -12 10 -14 10 -16 10 15 20 25 30 35 40 SNDR [dB] Important to realize • V 1   inpp that only comparator B cal  3 3 4 2  VOS B B power reduces cal 28

Impact of Calibration (2) -6 10 Flash ISSCC & VLSI 1997-2012 F lash65nm -8 10 F lash65nm,cal E min -10 10 P/f snyq [J] -12 10 -14 10 -16 10 15 20 25 30 35 40 SNDR [dB] 29

Ways to Approach E min (1) • Offset calibrate each comparator – Using trim-DACs [El-Chammas, VLSI 2010] 8 8 8 4 2 1 V outn V outp Decoder   D calp CAL V refn V inp V inn V refp CAL D caln  V lo V hi V lo V hi 30

Ways to Approach E min (2) • Find ways to reduce clock power • Example: resonant clocking (54% below CV 2 ) [Ma, ESSCIRC 2011] 31

Raison D'Être for Architectures Other than Flash… -6 10 -8 10 P/f s [J] -10 10 Flash Pipeline SAR  -12 Other 10 E flash65nm E flash32nm E min -14 10 20 30 40 50 60 70 80 90 100 110 SNDR [dB] 32

Pipeline ADC Align & Combine Bits D out V in SHA Stage 1 Stage n-1 Stage n Conversion occurs along • a cascade of stages V in1 V res1  G 1 Each stage performs a G 1 • coarse quantization and - computes its error (V res ) ADC DAC Stages operate • D 1 concurrently – Throughput is set by the speed of one single stage 33

Pipelining – A Very Old Idea 34

Typical Stage Implementation [Abo, 1999] Power goes here 35

Simplified Model for Energy Calculation C/2 m C C/2 C/4 2 2 2 2 MSB LSB • Considering the most basic case – Stage gain = 2  1 bit resolution per stage – Capacitances scaled down by a factor of two from stage to stage (first order optimum) – No front-end track-and-hold – Neglect comparator energy 36