Transistor Size Optimization Methodology for Logic Circuits - - PowerPoint PPT Presentation

Transistor Size Optimization Methodology for Logic Circuits Considering Variations caused by BTI and Process

TAU 2016 Thursday, March 10, 2016 Michitarou YABUUCHI, Kazutoshi KOBAYASHI Kyoto Institute of Technology

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Kobayashi Lab.

Summary

BTI (Bias Temperature Instability) and

process variations into consideration

Lifetime delay of logic path – 4.4% reduced Area – no overhead # of cells in library – 3x~

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Transistor Size Optimization Technique

Kobayashi Lab.

Background – Aging Degradation

Delay Time Spec. Timing Margin

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A B Y + + =

Kobayashi Lab.

Transistor Size Optimization

Conventional – initial delay based

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Wn/Wp [nm] Delay RMS [ps]

240/460 210/490 270/430 8.9 9.0 9.1 9.2 9.3

Lp = Ln = 45 nm Wp + Wn = 700 nm

= + 2

• Wp

Wn

Kobayashi Lab.

Impact of BTI on Inverter

Since 45 nm process – Both BTI Imbalance – dr and df degradation

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VDD VSS initial Input＝１

df increase by PBTI (NMOS degradation)

High Low

Slower to turn ON

aged High Input＝0

dr increases by NBTI (PMOS degradation)

Low

Slower to turn ON

Kobayashi Lab.

Purpose of This Study

Propose – lifetime delay based Key ideas

– Consider “lifetime experience” in logic gate design – Optimize transistor size to reduce “BTIGinduced variation”

Design cells for DF (Duty Factor) = 0, 0.5, 1

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Delay Time Margin reduced Efficient guardband

Kobayashi Lab.

Sizing – BTIGInduced Variation

Enlarge transistor size – reduce BTI variation

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∝ 1

• ⁄

: cnst.

=108 s =0.5 =45 nm Vth shift [mV] Standard Normal Quantile

Kobayashi Lab.

Results of Size Optimization

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240/460 210/490 270/430

Wn/Wp [nm]

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Delay RMS [ps]

Initial DF=1 DF=0

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DF=0.5

Lp = Ln = 45 nm Wp + Wn = 700 nm Prop. Conv.

Larger PMOS Larger NMOS

Kobayashi Lab.

Simulation Result – INV Chain

Lifetime delay – improved w/o area overhead

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Initial: 64.8 ps Lifetime: 76.6 ps Initial: 66.5 ps Lifetime: 73.2 ps 4.4% Conventional (initial based) Proposed (lifetime based) initial Lifetime (1) Lifetime (0)

Kobayashi Lab.

Conclusion

Transistor size optimization technique

– Conventional – initial delay based – Lead to large timing margin – Proposed – lifetime delay based – Path delay of inverter chain – improved by 4.4% – No requirement of area overhead – Support dependable and efficient chip designs

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Thank you for listening!

Kobayashi Lab.

BTI (Bias Temperature Instability)

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Permanent Component Recoverable Component

∆

• Stress

Relaxation PBTI (Positive BTI) on NMOS NBTI (Negative BTI) on PMOS 40 nm HKMG~ 65 nm~

• < 0
• > 0

Time

Kobayashi Lab.

Technique to Overcome Degradation

Adaptive Techniques

Body biasing Adaptive Supply Voltage

NonGadaptive Techniques

Sizing Strengthen

13 Overhead required Based on aging prediction

Kobayashi Lab.

Physics – Atomistic TrapGBased Model

Defect – capture and emit carriers

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: Defect (emission) : Defect (capture) Gate Dielectric Source Drain Gate ATGB Model

Kobayashi Lab.

Calculate

Distribution by BTI

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• P. Weckx et al, IRPS 2014

Input: transistor size, stress condition Output: ∆

• DefectGcentric distribution

Product of Nt and η Nt: number of defect (Poisson dist.) η: impact of single defect (Exp. Dist.)

Kobayashi Lab.

Physics – Scaling of BTI

Average – constant Deviation – area dependent (∝ 1

• ⁄

)

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Scaling Number of defect – decrease Impact of single defect – increase Defect in gate dielectric

Kobayashi Lab.

AgingGaware Library

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Signal Probability Profile AgingGaware Library Cells Gate Mapping Logic Simulation

• Tr. Size Optimization

Kobayashi Lab.

Optimization for MultiGinput Gate

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Wn/Wp [nm] Delay RMS [ps]

12 13 14 15 290/410 260/440 320/380 A=0, B=0 A=1, B=0 A=1, B=1 A=0, B=1 initial

A=0 B=0 A=0 B=1 A=1 B=0 A=1 B=1