Serial Parallel Multiplier Design in Quantum-dot Cellular Automata - PowerPoint PPT Presentation

Serial Parallel Multiplier Design in Quantum-dot Cellular Automata Heumpil Cho and Earl E. Swartzlander, Jr. Application Specific Processor Group Department of Electrical and Computer Engineering The University of Texas at Austin Austin, TX 78712 USA ARITH18 Application Specific Processor Group 1

Outline • Motivation • Quantum-dot Cellular Automata • Serial Multiplier Designs in QCA • Conclusions ARITH18 Application Specific Processor Group 2

Motivation Quantum-dot Cellular Automata (QCA) • Alternative to Transistor Technologies – Avoids High Power Consumption Due to Leakage Currents • Quantum-dot Cellular Automata (QCA) – Emerging Nanotechnology for Electronic Circuits • Introduced in 1993 • Freedom from Complicated Physics – High Density, Low Power Consumption, and Fast – Some Experimental Devices Have Been Created • Several QCA Circuits Have Been Proposed – Ripple Carry Adders, Barrel Shifters, and Memories – Complex Designs Rare • Key Characteristics – Inverters and 3-Input Majority Gates – Interconnect Consumes Time and Space • Difficult to Estimate Timing Until the Layout is Done – Signal Synchronization and Refresh • Wires Act as Latches • Best for Pipeline Architectures Without Feedback ARITH18 Application Specific Processor Group 3

QCA Technology Basic Quantum-dot Cell • Square Nanostructure – Each Cell • Has Four Quantum Dots • Can Possess a Single Electron per Dot • Charged With Two Electrons – Two Polarizations are Possible by Coulombic Repulsion Regular cells Quantom-dot Electron Tunnel Junction P=+1 P=-1 (Binary 1) (Binary 0) ARITH18 Application Specific Processor Group 4

QCA Technology Signal Propagation • Main Roles of Cells – Computation, Storage, and Communication – Wire Dominant Design • Series of QCA Cells – Act Like a Wire – Propagate the Signal • Clock Zones – Four Clock Phases – Control the Signal Flow – Cells Are Refreshed on Every Cycle ARITH18 Application Specific Processor Group 5

QCA Technology Fundamental Gates • Inverter – Conventional Gate • 3-Input Majority Gate M a b c ( , , ) a b b c c a = � + � + � • 2-Input AND/OR Gate – Implemented by Setting One Input to a Constant a b M a b ( , ,0) � = a b M a b ( , ,1) + = ARITH18 Application Specific Processor Group 6

QCA Technology Multi-Layer Wire Crossovers • Use Several Layers for Crossovers – 3D Structure • Pros and Cons + Area Efficient Design – Manufacturability Issues Layout Structure 0 1 0 1 ARITH18 Application Specific Processor Group 7

QCA Technology QCA Circuit Design Rules • Cell Size – Set at 20nm • Width and Height: 18nm • Quantum-dot Diameter: 5nm • Cell Center-to-Center Spacing: 20nm • Size Limit on Cells Per Clock Zone – Limit: 15 Cells • Proper Propagation Delay and Reliable Signal Transmission • Freedom for Routing and a Reasonable Clock Zone Size • Minimum Separation of Two Different Wires – The Width of Two Cells • Clock Increment Rule – Increment the Clock Zone at the Clock Arrangement Positions ARITH18 Application Specific Processor Group 8

Multiplier Design Serial Parallel Multiplier Designs in QCA • Multiplier Design Issues – A Parallel Multiplier is a Very Complex Circuit – Complex Circuits Often Incur Significant Delay • Simple Structure is Desirable – Serial-Parallel Multiplier Design Selected – Filter Design Methodology is Used ARITH18 Application Specific Processor Group 9

Multiplier Design Algorithmic Design • FIR Filter Design Example – Delay Operator: Z -1 1 n 1 n 1 Z x � x 1 , Z � Z Z � � + = = i i � – Filter Equation y b x b x b x b x b x L = + + + + + i 0 i 1 i 1 2 i 2 N 2 i N 2 N 1 i N 1 � � � � + � � + N 1 N 1 N 1 � � � � � k k b x b Z x b Z x � � � � � = = = � � k i k k i k i � � � k 0 k 0 k 0 = = = … Z -1 Z -1 x i … b N-1 b N-2 b 1 b 0 … y i + + + ARITH18 Application Specific Processor Group 10

Multiplier Design Pipelined FIR Filter Network • Pipelined FIR Filter Output (Right-to-Left Structure) 1 3 1 3 1 � � � � ( N 1) ( N 2) � � � � � � � ( 0 ) Z b Z Z b Z Z b Z x 2 2 2 2 L 2 = + + + � � � � N 1 N 2 0 i � � � � � � � � N N N � � � ( N 1) ( N 2) Z b Z x Z b Z x Z b x 2 � � 2 � � 2 L = + + + N 1 i N 2 i 0 i � � N N 1 � � � � k Z b Z x 2 � � = � � k i � � k 0 = N … Z -3/2 Z -3/2 x i � Z y 2 = i … b N-1 b N-2 b 1 b 0 … Z -N/2 y i Z -1/2 Z -1/2 Z -1/2 + + + ARITH18 Application Specific Processor Group 11

Multiplier Design Redirected FIR Filter Network • General Structure (Right-to-Right Structure) … Z -1 Z -1 x i … b N-1 b N-2 b 1 b 0 … + + + y i 1 1 N 1 � � � � � k Z y Z b Z � x 2 2 � • Pipelined Structure = � � i k i � � k 0 = 1 k k N 1 � � � … Z -1/2 Z -1/2 x i � � � Z b Z Z x 2 � 2 2 = � � k i � � k 0 = … b N-1 b N-2 b 1 b 0 1 k k N 1 � � � � � � Z Z b Z x 2 � 2 2 = … � � Z -1/2 Z -1/2 Z -1/2 Z -1/2 y i + + + k i � � k 0 = ARITH18 Application Specific Processor Group 12

Multiplier Design Multiplication Signal Flows • Unsigned Number Multiplication – Bit Product Matrix and Signal Flow of Right-to-Left Structure a 3 a 2 a 1 a 0 Time X b 3 b 2 b 1 b 0 0 0 0 0 a 3 b 0 a 2 b 0 a 1 b 0 a 0 b 0 0 0 0 0 a 3 b 0 a 2 b 0 a 1 b 0 a 0 b 0 0 S a 3 b 1 a 2 b 1 a 1 b 1 a 0 b 1 t 0 0 0 0 0 0 0 a 3 b 1 a 2 b 1 a 1 b 1 a 0 b 1 0 0 0 0 a 3 b 2 a 2 b 2 a 1 b 2 a 0 b 2 0 0 0 0 a 3 b 2 a 2 b 2 a 1 b 2 a 0 b 2 0 0 0 e a 3 b 3 a 2 b 3 a 1 b 3 a 0 b 3 0 0 0 0 0 a 3 b 3 a 2 b 3 a 1 b 3 a 0 b 3 0 0 0 0 p p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 p 7 p 6 p 5 p p 3 p 2 p 1 p p 7 4 0 t 13 t 12 t 11 t 10 t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 t -1 t -2 t -3 – Bit Product Matrix and Signal Flow of Right-to-Right Structure a 3 a 2 a 1 a 0 Time X b 3 b 2 b 1 b 0 t 12 t 11 t 10 t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 t -1 t -2 t -3 p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 p 1 p 0 p 7 p 6 p 5 p 4 p 3 p 2 a 1 b 0 a 0 b 0 0 0 0 0 a 3 b 0 a 2 b 0 a 1 b 0 a 0 b 0 0 0 0 0 a 3 b 0 a 2 b 0 S a 3 b 1 a 2 b 1 a 1 b 1 a 0 b 1 t a 0 b 1 0 0 0 0 0 0 0 0 a 3 b 1 a 2 b 1 a 1 b 1 0 0 0 0 a 3 b 2 a 2 b 2 a 1 b 2 a 0 b 2 0 0 0 0 a 3 b 2 a 2 b 2 a 1 b 2 a 0 b 2 e a 3 b 3 a 2 b 3 a 1 b 3 a 0 b 3 0 0 0 0 0 0 0 a 3 b 3 a 2 b 3 a 1 b 3 a 0 b 3 0 p ARITH18 Application Specific Processor Group 13

Multiplier Design Network Diagrams-I • Right-to-Left Carry Shift Multiplication (CSM) … Z -7/4 Z -7/4 a i … b N-1 b N-2 b 1 b 0 … Z -3N/4 p i Z -3/4 + Z -3/4 + + Z -3/4 + Z -1 0 Z -1/4 Z -1/4 • Right-to-Left Carry Delay Multiplication (CDM) … Z -3/2 Z -3/2 a i … b N-1 b N-2 b 1 b 0 … Z -N/2 p i Z -1/2 + Z -1/2 + + Z -1/2 Z -1 Z -1 Z -1 ARITH18 Application Specific Processor Group 14

Multiplier Design Network Diagrams-II • Right-to-Right Carry Shift Multiplication (CSM) … Z -1/4 Z -1/4 a i … b N-1 b N-2 b 1 b 0 … Z -1 + Z -3/4 + + Z -3/4 + Z -3/4 Z -3/4 p i Z -1/4 Z -1/4 0 • Right-to-Right Carry Delay Multiplication (CDM) … Z -1/2 Z -1/2 a i … b N-1 b N-2 b 1 b 0 … Z -1/2 + + Z -1/2 + Z -1/2 Z -1/2 p i Z -1 Z -1 Z -1 ARITH18 Application Specific Processor Group 15

Multiplier Design QCA Multiplication Diagrams • Multiplication Networks for QCA – One Clock Zone Delay: D -1 (D -4 =Z -1 ) • Filter Network Transformation Using D Operators … D -6 D -6 D -1 a i … b N-1 b N-2 b 1 b 0 D -1 D -1 D -1 D -1 … D -2N-2 p i D -2 + D -2 + + D -2 … D -2 D -2 D -1 a i … b N-1 b N-2 b 1 b 0 D -1 D -1 D -1 D -1 … D -2 D -2 D -2 D -4 p i + + + ARITH18 Application Specific Processor Group 16

Multiplier Design Right-to-Left Networks • Equations ( 7 j 2 3 1 ) ( s c , ) Addition b D � � a D s , � , D c � = ij ij j i i j ( 1) i j ( 1) � + ( ) Addition b a , s , c = j i 7 j 2 ( i 3)( j 1) ( i 1)( j 1) � � � � � + ( 6 j 2 2 4 ) ( s c , ) Addition b D a D s , , D c � � � � = ij ij j i i j ( 1) ij � ( ) Addition b a , s , c = j i 6 j 2 ( i 2)( j 1) ( i 4) j � � � � � CSM Network CDM Network … … D -7 D -7 D -1 D -6 D -6 D -1 a i a i … … b N-1 b N-2 b 1 b 0 b N-1 b N-2 b 1 b 0 D -1 D -1 D -1 D -1 D -1 D -1 D -1 D -1 … … D -2N-2 p i D -2 + D -2 + + D -2 D -3N-2 p i D -3 + D -3 + + D -3 + D -4 D -1 D -1 0 D -4 D -4 D -4 ARITH18 Application Specific Processor Group 17