Self-Aligned InGaAs FinFETs with 5-nm Fin-Width and 5-nm Gate-Contact Separation Alon Vardi, Lisa Kong, Wenjie Lu, Xiaowei Cai, Xin Zhao, Jesús Grajal* and Jesús A. del Alamo Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA, U.S.A *ETSI Telecomunicación, Universidad Politécnica de Madrid, Madrid, Spain Dec. 5, 2017 Sponsors: DTRA (HDTRA 1‐14‐1‐0057) NSF E3S STC (grant #0939514) Lam Research Korea Institute of Science and Technology 1
FinFETs Intel Si Trigate MOSFETs Double gate Tri gate FinFETs used in state‐of‐the‐art Si CMOS • improved short‐channel effects • smaller footprint • but… higher parasitics 2
Si and InGaAs FinFETs normalized by gate periphery 3.5 3.0 Planar Si 2.5 32 nm g m [mS/ m] Si FinFETs 2.0 14 nm 22 nm 1.5 1.0 0.5 0.0 // 0 10 20 30 Planar W f [nm] • Si planar FinFET: performance ↓ 3
Si and InGaAs FinFETs normalized by gate periphery normalized by fin footprint AR=H c /W f 3.5 20 5.3 3.0 W f Si FinFETs (V DD =0.8 V) Planar Si 15 2.5 32 nm 4.3 g m /W f [mS/ m] g m [mS/ m] Si FinFETs 2.0 H c 14 nm 10 22 nm 1.5 1.0 5 0.5 0.0 // 0 // 0 10 20 30 Planar 0 10 20 30 Planar W f [nm] W f [nm] • Si planar FinFET: performance ↓, performance per footprint ↑ • Key challenge for FinFETs efficient transport on sidewalls 4
Si and InGaAs FinFETs normalized by gate periphery normalized by fin footprint Planar InGaAs (V DD =0.5 V) Lin, EDL2016 AR=H c /W f 3.5 20 5.3 3.0 W f Si FinFETs (V DD =0.8 V) Planar Si 15 2.5 32 nm 4.3 g m /W f [mS/ m] g m [mS/ m] Si FinFETs 2.0 H c 14 nm 10 22 nm 1.5 1.0 5 0.5 0.0 // 0 // 0 10 20 30 Planar 0 10 20 30 Planar W f [nm] W f [nm] • III‐V planar ~ Si planar 5
Si and InGaAs FinFETs normalized by gate periphery normalized by fin footprint Planar InGaAs (V DD =0.5 V) Lin, EDL2016 Target: W F =5 nm 3.5 3.5 20 5.3 3.0 3.0 W f Si FinFETs (V DD =0.8 V) Planar Si 15 2.5 2.5 32 nm 4.3 g m /W f [mS/ m] g m [mS/ m] g m [mS/ m] Si FinFETs Si FinFETs 5.7 2.0 2.0 H c 14 nm 10 22 nm InGaAs FinFETs 1.5 1.5 1.0 1.0 5 0.5 0.5 0.0 0.0 // 0 // 0 0 10 10 20 20 30 30 Planar Planar 0 10 20 30 Planar W f [nm] W f [nm] W f [nm] • g m (III‐V FinFETs) < g m (Si) • Target of W f =5 nm yet to be demonstrated 6
Si and InGaAs FinFETs normalized by gate periphery normalized by fin footprint Planar InGaAs (V DD =0.5 V) Lin, EDL2016 Target: W F =5 nm 3.5 20 5.3 3.0 W f Si FinFETs (V DD =0.8 V) Planar Si 15 2.5 32 nm 4.3 g m /W f [mS/ m] g m [mS/ m] Si FinFETs 5.7 2.0 H c 14 nm InGaAs FinFETs 10 22 nm InGaAs FinFETs 1.5 1.0 5 0.5 0.0 // 0 // 0 10 20 30 Planar 0 10 20 30 Planar W f [nm] W f [nm] • III‐V FinFET: W f < 20 nm g m ↓ • Challenge: Improve III‐V sidewall conductivity 7
MIT InGaAs FinFET’s Gen. #2 vs. #1 Mo Gen #1: SiO 2 L f,g • Wet cap recess Mo/W 60 nm • 3 Digital etch cycles SiO 2 InGaAs channel Mo/W InP • 40 nm channel height InGaAs ~20 nm • δ‐doping InAlAs Wet recess Gen. #1: Vardi et al., VLSI 2016, EDL 2016 Gen #2: Mo • Dry cap recess HSQ SiO 2 L f SiO 2 • 5 Digital etch cycles Mo/W HfO 2 Mo/W L g • 50 nm channel cap cap 40nm ~5 nm Cap • Fin‐top passivation InGaAs channel • Remove δ‐doping (in 2 nd stage) Channel InAlAs Dry+DE recess Gen. #2: This work 8
Process Technology: contact-first W direction L g direction SiO 2 Mo/W InP stopper InGaAs cap InGaAs channel ‐Doping InAlAs Lin, IEDM 2013 Lu, EDL 2014 Contact deposition Vardi, EDL 2014 • Yield R C < 10 Ω∙µm 9
Dry+Digital Etch cap recess W direction L g direction L f Mo/W L g InP stopper SiO 2 InGaAs cap Mo/W InGaAs channel 40nm ~5 nm Cap ‐Doping InAlAs Channel Dry+DE recess Contact etch Reactive ion etching Digital etching • No metal pullback (Lin, IEDM 2013) • III‐V cap pullback only during digital etch 10
Dry+Digital Etch fin definition W f HSQ W f direction Fin H c H f Zhao, EDL 2014, Vardi, VLSI 2016 L g direction HSQ SiO 2 L g 8 nm Mo/W cap 170 nm InGaAs channel InAlAs 100 nm Fin etch Cap recess fin • BCl 3 /SiCl 4 /Ar RIE + 5 DE cycles : smooth, vertical sidewalls and high aspect ratio (>10) 11
Gate stack - Double gate FinFET W direction HSQ W f Top fin passivation HfO 2 H c H f Mo L g direction HSQ SiO 2 L g Mo/W InP stopper InGaAs cap InGaAs channel ‐Doping InAlAs Cap recess Contact deposition Fin etch Gate stack fin • HSQ stays on top of fins double‐gate FinFET • Gate oxide – 3 nm HfO 2 12 (vs. 2.3 nm in EDL2016)
Device cross section FIB cross section in L g direction TEM of finished device in W f direction 5 nm • Fin pitch: 200 nm • 10‐200 fins/device • W f : 5‐25 nm • L g : 30 nm – 5 µm • Contact to channel separation set by DE : ~ 5 nm 13
Electrical characteristics: W f =5 nm, L g =50 nm 700 250 1E-3 V GS =-0.2 to 0.5 V L g =50 nm g m,max =600 µS/µm V DS =500 mV V DS =0.5 V 600 V GS =0.1 V W f =5 nm L g =50 nm 1E-4 200 50 mV 500 W f =5 nm 1E-5 S sat =100 mV/dec 150 g m [ S/ m] 400 I d [ A/ m] I d [A/ m] S lin =73 mV/dec 1E-6 300 100 1E-7 200 50 1E-8 100 0 0 1E-9 0.0 0.1 0.2 0.3 0.4 0.5 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 -0.2 0.0 0.2 0.4 0.6 0.8 V GS [V] V GS [V] V GS [V] Normalized by gate periphery • Well behaved devices with W f =5 nm 14
On/Off performance: fin width scaling 2.0 V DS = 0.5 V V DS = 0.5 V 180 1.5 S sat [mV/dec] 120 g m [mS/ m] 1.0 60 0.5 L g =40‐60 nm L g =40‐60 nm 0 0.0 0 5 10 15 20 25 0 5 10 15 20 25 W f [nm] W f [nm] • W f ↓: S sat ↓ • W f ↓: g m ↓ 15
To improve Off performance: remove δ-doping Gen. #2 ‐ Undoped Gen. #2 ‐ δ‐doped Gen. #1 Mo Mo HSQ HSQ SiO 2 SiO 2 Mo Mo cap cap cap cap InGaAs InGaAs ‐Doping InAlAs Extrinsic area fin • δ‐doping R sd ↓ • Dry gate recess allows to remove δ‐doping • Impact on the intrinsic fin transport 16
W F =5 nm FinFET: Electrical characteristics: δ-doped vs. undoped 700 250 1E-3 V GS =-0.2 to 0.5 V L g =50 nm g m,max =600 µS/µm V DS =500 mV V DS =0.5 V 600 V GS =0.1 V W f =5 nm L g =50 nm g m,max =500 µS/µm 1E-4 200 50 mV 500 W f =5 nm 1E-5 S sat =100 mV/dec 150 g m [ S/ m] 400 I d [ A/ m] I d [A/ m] S lin =73 mV/dec 1E-6 300 100 1E-7 200 S sat =75 mV/dec 50 doped 1E-8 100 S lin =65 mV/dec undoped 0 0 1E-9 0.0 0.1 0.2 0.3 0.4 0.5 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 -0.2 0.0 0.2 0.4 0.6 0.8 V GS [V] V GS [V] V GS [V] Normalized by gate periphery Undoped fins: • better OFF performance • Undoped Similar ON performance 17
Electrical characteristics: δ-doped vs. undoped 2.0 V DS = 0.5 V 180 Undoped Undoped -doped -doped 1.5 S sat [mV/dec] 120 g m [mS/ m] 1.0 60 0.5 L g =40‐60 nm L g =40‐60 nm 0 0.0 0 5 10 15 20 25 0 5 10 15 20 25 W f [nm] W f [nm] • Undoped fin: improved electrostatics • For W f <20 nm undoped‐fin ON performance also better 18
Electrical characteristics: V T rolloff δ‐doped Undoped W f =5 nm 0.5 0.5 W f =9 W F ↓ 0.4 0.4 W f =13 W f =17 0.3 0.3 W F ↓ W f =21 0.2 0.2 W f =25 V T,lin [V] V T,lin [V] 0.1 0.1 0.0 0.0 -0.1 -0.1 -0.2 -0.2 0 200 400 600 0 200 400 600 L g [nm] L g [nm] Undoped fins smaller variation of V T with W F Improved V T rolloff 19
Benchmarking normalized by gate periphery 3.5 Undoped 3.0 -doped 2.5 InGaAs FinFETs g m [mS/ m] Si FinFETs 2.0 H c H c 1.5 1.0 0.5 0.0 0 10 20 30 40 W f [nm] • Systematic g m degradation for W f < 15 nm for both δ‐doped and undoped structures • No improvement from increased #DE cycles • Higher EOT lower g m w.r.t. to Gen. 1 20
Benchmarking normalized by gate periphery Target: W F =5 nm 3.5 20 W f Undoped 5.3 3.0 Si FinFETs (V DD =0.8 V) -doped 15 2.5 4.3 10 g m /W f [mS/ m] Undoped InGaAs FinFETs g m [mS/ m] Si FinFETs 2.0 H c H c -doped 10 1.5 1.0 5 InGaAs FinFETs 0.5 0.0 0 0 10 20 30 40 0 5 10 20 30 40 W f [nm] W f [nm] • Record W f with good electrical performance • Approaching Si FinFETs even at V DD =0.5 V • Record AR=10 21
Long-channel Mobility vs. W f Capacitance measured @ 1GHz δ‐doped undoped W f =25 nm W f =9 nm • Strong µ degradation as W f ↓ • W f < 10 nm µ independent of n l 22
Simulations – charge distribution ON state: n l =3x10 7 cm ‐1 W f =25 nm undoped δ‐doped y • Undoped fin: better use of sidewalls • δ‐doped fin: conduction close to lower facet of channel 23
Simulations – charge distribution ON state: n l =3x10 7 cm ‐1 W f =9 nm W f =25 nm undoped undoped δ‐doped δ‐doped y • Narrow fin: volume inversion in both δ‐doped and undoped fins 24
Simulations – capacitance ON state: n l =3x10 7 cm ‐1 (V GT ~ 0.4V) W f =9 nm W f =25 nm undoped undoped undoped undoped Simulation Simulation δ‐doped δ‐doped δ‐doped δ‐doped E s (y) y Simulation Simulation • Reasonable agreement between measurement and simulations extract n l ‐ E s relation 25
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