Routability-driven Placement Algorithm for Analog Integrated Circuits Cheng-Wu Lin, Cheng-Chung Lu, Jai-Ming Lin, and Soon-Jyh Chang March 27, 2012 Department of Electrical Engineering National Cheng Kung University, Tainan, Taiwan
Outline Outline Introduction to Analog Placement Routability-driven Analog Placement Congestion Estimation Placement Expansion Proposed Placement Flow Experimental Results Conclusion 2
Analog Placement Considerations Analog Placement Considerations Basic constraints Matching interdigitated placement, common-centroid placement Symmetry symmetric placement Proximity adjacent placement Substrate Well Other considerations Thermal effects, stress gradients, etc. M 5 M 4 M 3 M M M M M M 2 1 1 2 3 4 M 2 M M M M M M M M M M M 1 1 2 1 2 1 2 2 1 1 2 Interdigitated Common-centroid Proximity constraint Symmetry constraint placement placement 3
Analog Placement Approaches Analog Placement Approaches Constructive method Generate placement according to schematic topology [Mehranfar, JSSC ’91] or signal paths [Long et al., ASP-DAC’06] M5 M5 M7 、 M10 M7 、 M10 M7 、 M10 M7 、 M10 W W W W V B 1 V B 1 M 10 M 10 M 5 M 5 2 2 2 2 ○ ○ M 7 M 7 M1 、 M2 M1 、 M2 ● ● M6 、 M9 M6 、 M9 V IP V IP V IN V IN M6 、 M9 M6 、 M9 M 2 M 2 ○ ○ ○ ○ M 1 M 1 W W W W V ON V ON V OP V OP M11 M3 、 M4 M8 M3 、 M4 M11 M8 2 2 2 2 ○ ○ ● ● ● ● ● ● ● ● ● ● ● ● ○ ○ M 11 M 11 M 8 M 8 C C 2 C C 2 C C 1 C C 1 M 3 M 3 M 4 M 4 ● ● M 9 M 9 M 6 M 6 ○ ○ V B 2 V B 2 C C1 and C C2 C C1 and C C2 4
Analog Placement Approaches Analog Placement Approaches Constructive method Generate placement according to schematic topology [Mehranfar, JSSC ’91] or signal paths [Long et al., ASP-DAC’06] 4
Analog Placement Approaches Analog Placement Approaches Constructive method Generate placement according to schematic topology [Mehranfar, JSSC ’91] or signal paths [Long et al., ASP-DAC’06] Deterministic algorithm Enumerate all possible placements for the basic module sets, and then combine these placements hierarchically [Strasser et al., ICCAD’08] 4
Analog Placement Approaches Analog Placement Approaches Constructive method Generate placement according to schematic topology [Mehranfar, JSSC ’91] or signal paths [Long et al., ASP-DAC’06] Deterministic algorithm Enumerate all possible placements for the basic module sets, and then combine these placements hierarchically [Strasser et al., ICCAD’08] 4
Analog Placement Approaches Analog Placement Approaches Constructive method Generate placement according to schematic topology [Mehranfar, JSSC ’91] or signal paths [Long et al., ASP-DAC’06] Deterministic algorithm Enumerate all possible placements for the basic module sets, and then combine these placements hierarchically [Strasser et al., ICCAD’08] Statistical algorithm Apply simulated annealing (SA) algorithm with floorplan representations 4
Representations for Analog Placement Representations for Analog Placement Topological representation is a popular method for modern VLSI design Smaller solution space (compared with absolute representation) Need specific techniques to deal with placement constraints Previous work of handling symmetry constraint Sequence-pairs [Balasa & Lampaert, DAC’99] O-trees [Pang et al., DAC’00] Binary trees [Balasa, ICCAD’00] TCG-S [Lin et al., ASP-DAC’05] CBL [Liu et al., ASP-DAC’07] Previous work of tackling common-centroid constraint C-CBL [Ma et al., ICCAD’07] B*-trees [Strasser et al., ICCAD’08] Sequence-pairs [Xiao & Young, ASP-DAC’09] 5
Routability-driven Analog Placement Routability-driven Analog Placement One of the objective function in SA algorithm is to minimize chip area, which makes blocks compact to the lower-left corner For analog design, a compact placement is not practical Routing over the active areas of analog devices is usually avoided to reduce parasitics and cross-talk effects Reserve enough spaces between the devices for laying out wires 6
Review of Congestion-aware Placement Review of Congestion-aware Placement Congestion-aware placement for analog circuits [Xiao et al., ICCAD’10] Whole placement region is divided into an n n mesh, and vertical and horizontal congestions are estimated for each room Rooms are expanded column-by-column and row-by-row based on the congestion map Symmetry constraint must be satisfied after placement expansion Non-symmetry module Symmetry group 5 5 mesh Column expansion Symmetry constraint Symmetry axis Symmetry axis is violated! 7
Problem Formulation Problem Formulation Given a set of devices and topological placement constraints The active areas of all devices are considered as routing blockages Routing congestion in the resulting placement P is minimized All topological constraints are satisfied in the resulting placement P Cost function ( P ): ( P ) = A P + W P + C P A P : bounding-rectangle area of the placement W P : total wire length measured by half-perimeter estimation C P : estimation of routing congestion 8
Overview of Our Placement Flow Overview of Our Placement Flow Input devices, netlist, and topological placement constraints Generate a compact placement based on ASF-B* -trees and HB* -trees Estimate routing congestion Expand congested regions No Minimum cost? Yes Done 9
Congestion Estimation Congestion Estimation The way to predict congestion accurately is to use the same technique and parameters in both congestion estimation and global routing [Pan & Chu, ICCAD’06] Congestion-driven Steiner tree construction can be used for congestion estimation and global routing Previous work: FastRoute [Pan & Chu, ICCAD’06] , NTHU-Route [Chang et al., ICCAD’08] 1. Use FLUTE to generate the Steiner 1. minimal trees for all nets 2. Route two-pin nets using L-shaped Congestion map generation 2. pattern routing 3. Generate congestion map from the 3. routing demand Congestion-driven Steiner tree construction Route two-pin nets using pattern routing and maze routing 10
Congestion Estimation Congestion Estimation The way to predict congestion accurately is to use the same technique and parameters in both congestion estimation and global routing [Pan & Chu, ICCAD’06] Congestion-driven Steiner tree construction can be used for congestion estimation and global routing Previous work: FastRoute [Pan & Chu, ICCAD’06] , NTHU-Route [Chang et al., ICCAD’08] Reconstruct Steiner tree for each net Congestion map generation according to the congestion map Congestion-driven Steiner tree construction Route two-pin nets using pattern routing and maze routing 10
Congestion Estimation Congestion Estimation The way to predict congestion accurately is to use the same technique and parameters in both congestion estimation and global routing [Pan & Chu, ICCAD’06] Congestion-driven Steiner tree construction can be used for congestion estimation and global routing Previous work: FastRoute [Pan & Chu, ICCAD’06] , NTHU-Route [Chang et al., ICCAD’08] Reconstruct Steiner tree for each net Congestion map generation according to the congestion map Congestion-driven Steiner tree construction Route two-pin nets using pattern routing and maze routing 10
Congestion Estimation Congestion Estimation The way to predict congestion accurately is to use the same technique and parameters in both congestion estimation and global routing [Pan & Chu, ICCAD’06] Congestion-driven Steiner tree construction can be used for congestion estimation and global routing Previous work: FastRoute [Pan & Chu, ICCAD’06] , NTHU-Route [Chang et al., ICCAD’08] Reconstruct Steiner tree for each net Congestion map generation according to the congestion map Congestion-driven Steiner tree construction Route two-pin nets using pattern routing and maze routing 10
Congestion Estimation Congestion Estimation The way to predict congestion accurately is to use the same technique and parameters in both congestion estimation and global routing [Pan & Chu, ICCAD’06] Congestion-driven Steiner tree construction can be used for congestion estimation and global routing Previous work: FastRoute [Pan & Chu, ICCAD’06] , NTHU-Route [Chang et al., ICCAD’08] Proposed congestion map generation: Congestion map generation Congestion-driven Steiner tree construction Route two-pin nets Generate congestion map using L-shaped pattern routing from the routing demand 10
Congestion Map Generation with Analog Devices Congestion Map Generation with Analog Devices Grid graph model for global routing: Global bins Modules Global edges Grid graph model Since the active areas of all devices are considered as routing blockages, we reduce global edge capacities of a bin if the bin is occupied by some devices 11
Congestion Map Generation with Analog Devices Congestion Map Generation with Analog Devices a s c e 2 , d e 2 c e 2 * , d e 2 if d e > c e *, overflow e = d e – c e * c e 1 , d e 1 c e 1 * , d e 1 otherwise overflow e = 0 Edge capacity: c e c e 1 * = 0 a c e 2 * = c e 2 Routing demand: d e s 12
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