Benefits of Asynchronous Control for Analog Electronics: Multiphase Buck Case Study Danil Sokolov, Vladimir Dubikhin, Victor Khomenko, David Lloyd 8 , Andrey Mokhov, Alex Yakovlev Newcastle University, UK 8 Dialog Semiconductor, UK
Outline • Motivation • Basic buck converter • A4A design flow • A2A components • W ORKCRAFT design automation • Design of multiphase buck converter • Experimental results 2 / 21
Motivation: Little digital control for analog electronics IP cores (big digital) Legend: level shifters digital A2D D2A synchronisers sensors power analog converters sensor/timing/energy infrastructure sanitisers time bands slow fast local scope for control for analog layer (little digital) design automation Analog and digital electronics are becoming more intertwined • Analog domain becomes more complex and itself needs digital control • 3 / 21
Motivation: Power electronics context Efficient implementation of power converters is paramount • Extending the battery life of mobile gadgets • Reducing the energy bill for PCs and data centres • (5% and 3% of global electricity production respectively) Need for responsive and reliable control circuitry • Millions of control decisions per second for years • An incorrect decision may permanently damage the circuit • Need for EDA ( little digital vs big digital design flow) • RTL flow is optimised for synchronous data processing • Ad hoc asynchronous solutions are prone to errors and cannot be verified • 4 / 21
Basic buck converter under-voltage V_ref Phase diagram specification: over-current I_max V_pmos gp_ack analog no ZC late ZC early ZC buck I_max gp PMOS ON digital N NMOS ON PMOS N Current NMOS ON NMOS OFF O oc O F PMOS OFF F S PMOS OFF F S F control O O O O M S M S P O uv O P M PMOS OFF M N N NMOS OFF I_0 zc NMOS R_load UV OC UV ZC OC ZC UV OC gn Time gn_ack V_nmos I_0 zero-crossing Buck conditions: Operating modes: under-voltage (UV) no zero-crossing • • over-current (OC) late zero-crossing • • zero-crossing (ZC) early zero-crossing • • 5 / 21
Basic buck converter: Synchronous design RTL description: Design Compiler synthesis result: nrst module control (clk, nrst, oc, uv, zc, gp_ack, gn_ack, gp, gn); . input clk, nrst, uv, oc, zc, gp_ack, gn_ack; gp_ack . output reg gp, gn; RB gn_ack gp . always @( posedge clk or negedge nrst) begin D Q CK . if (nrst == 0) begin oc . gp <= 0; gn <= 1; uv . end else case ({gp_ack, gn_ack}) zc . 2’b00: if (uv == 1) gp <= 1; else if (oc == 1) gn <= 1; . 2’b10: if (oc == 1) gp <= 0; SB gn . 2’b01: if (uv == 1 || zc == 1) gn <= 0; D Q CK . endcase . end .endmodule clk Asynchronous inputs need to be synchronised (latency penalty) • If clock is slow, the control is unresponsive to the buck changes • If clock is fast, it burns energy when the buck is inactive • 6 / 21
Basic buck converter: Asynchronous design Formal specification: Hazard-free implementation: Formal specification using Signal Transition Graphs – similar to Petri nets • Verifiable hazard-free implementation – correct for any gate delays • Prompt reaction time to the buck changes – latency of a complex gate • 7 / 21
Asynchronous control for Analog electronics (A4A) design flow libraries and specification and synthesis verification design guidelines and validation informal design intent (waveforms, phase diagrams) manual effort architectural decomposition design concepts and component formalisation formal specification of components sanity check (signal transition graph) (Punf, MPSat) logic synthesis & technology mapping verification report gate library (violation traces) (Petrify, Punf, MPSat) functional verification hazard-free components (PComp, Punf, MPSat) (Verilog netlist) system integration reachability report A2A interfaces (Workcraft) (hazard traces) little digital asynchronous controller timing verification (Verilog netlist) (PrimeTime) conventional design flow signoff report offline testing features (timing violations) and place & route 8 / 21
Library of analog-to-asynchronous (A2A) interface components Interface analog world of dirty signals • Provide hazard-free sanitised digital signals • Basic A2A interface components • WAIT / WAIT0 – wait for analog input to become high / low and • latch it until explicit release signal RWAIT / RWAIT0 – modification of WAIT / WAIT0 with a possibility • to persistently cancel the waiting request WAIT01 / WAIT10 – wait for a rising / falling edge • Advanced A2A interface components • WAIT2 – combination of WAIT and WAIT0 to wait for high and low • input values, one after the other WAITX – arbitrate between two non-persistent analog inputs • WAITX2 – behaves as WAITX in the rising phase and as WAIT0 in the falling phase • 9 / 21
W ORKCRAFT design automation – http://workcraft.org/ 10 / 21
Multiphase buck converter under-voltage V_ref Phases – pairs of power regulating transistors • over-current I_max (I_0) V_pmos Each phase operates as a basic buck basic converter gp_ack • analog oc Phases are activated sequentially buck • gp digital PMOS Active phases may overlap control • uv NMOS R_load gn More operating modes • zc gn_ack V_nmos Over-voltage (OV) – sink energy excess • I_0 (I_neg) zero-crossing High-load (HL) – boost the power • I_max (I_0) multiphase converter V_pmos gp_ackN ocN Transistor min ON times • gpN PMOS[N] hl PMOS transistor: PMIN delay • NMOS transistor: NMIN delay ov • NMOS[N] PMOS at first cycle: PMIN+PEXT delay gnN • zcN gn_ackN V_nmos I_0 (I_neg) V_max over-voltage V_min high-load 11 / 21
Multiphase buck converter: Synchronous control Two clocks: phase activation (slow) and sampling (fast) • Need for multiple synchronizers (grey boxes) – latency overheads, risk of metastability • Conventional RTL design flow for PHASE_ACTIVATOR and SYNC_PHASE_CTRL components • 12 / 21
Multiphase buck converter: Asynchronous control Token ring architecture, no need for phase activation clock • No need for synchronisers – all signals are asynchronous • A4A design flow for ASYNC_PHASE_CTRL component • 13 / 21
Multiphase buck converter: Asynchronous phase control - analog-asynchronous interfaces l asymmetric delays elements - synthesised hazard-free components 14 / 21
Multiphase buck converter: Asynchronous phase control - analog-asynchronous interfaces l asymmetric delays elements - synthesised hazard-free components 14 / 21
Multiphase buck converter: Asynchronous phase control - analog-asynchronous interfaces l asymmetric delays elements - synthesised hazard-free components 14 / 21
Multiphase buck converter: Asynchronous phase control - analog-asynchronous interfaces l asymmetric delays elements - synthesised hazard-free components 14 / 21
Multiphase buck converter: Asynchronous phase control - analog-asynchronous interfaces l asymmetric delays elements - synthesised hazard-free components 14 / 21
Multiphase buck converter: Asynchronous phase control - analog-asynchronous interfaces l asymmetric delays elements - synthesised hazard-free components 14 / 21
Multiphase buck converter: Design of asynchronous components Token control Hazard-free implementation • • Formal specification • 15 / 21
Experimental results: Simulation setup Verilog-A model of the 4-phase buck • Control implemented in TSMC 90nm • AMS simulation in C ADENCE NC-V ERILOG • Synchronous design • Phase activation clock – 5MHz • Clocked FSM-based control – 100MHz, 333MHz, 666MHz, 1GHz • Sampling and synchronisation • Asynchronous design • Phase activation – token ring with 200ns timer (= 5MHz) • Event-driven control (input-output mode) • Waiting rather than sampling (A2A components) • 16 / 21
Experimental results: Simulation waveforms TIME ( ✁ s) 0 1 2 3 4 5 6 7 8 9 10 synchronous @ 333MHz phase_clk fsm_clk 3 3.3V 0.43V 2 V_load (V) 1 startup high load normal load normal load 0 hl uv ov act 0.24A phase 0.2 0.1 I_coil (A) 0 -0.1 3 3.3V 0.36V 2 asynchronous V_load (V) 1 startup high load normal load normal load 0 hl uv ov get & !pass phase 0.2 0.21A 0.1 I_coil (A) 0 -0.1 17 / 21
Experimental results: Simulation waveforms TIME ( μ s) 0 1 2 3 4 5 6 7 8 9 10 synchronous @ 333MHz phase_clk fsm_clk 3 3.3V 0.43V 2 V_load (V) 1 startup high load normal load normal load redundant 0 hl switching uv ov activity of act two clocks 0.24A phase 0.2 0.1 I_coil (A) 0 -0.1 3 3.3V 0.36V 2 asynchronous V_load (V) 1 startup high load normal load normal load 0 hl uv ov get & !pass phase 0.2 0.21A 0.1 I_coil (A) 0 -0.1 17 / 21
Experimental results: Simulation waveforms TIME ( μ s) 0 1 2 3 4 5 6 7 8 9 10 synchronous @ 333MHz phase_clk fsm_clk 3 3.3V 0.43V 2 V_load (V) 1 startup high load normal load normal load 0 hl uv ov act 0.24A phase 0.2 0.1 I_coil (A) 0 -0.1 unnecessary activation 3 3.3V 0.36V 2 asynchronous of phases V_load (V) 1 startup high load normal load normal load 0 hl uv ov get & !pass phase 0.2 0.21A 0.1 I_coil (A) 0 -0.1 17 / 21
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