AN ASYNCHRONOUS DIVIDER IMPLEMENTATION Navaneeth Jamadagni and Jo - PowerPoint PPT Presentation

Asynchronous Research Center Asynchronous Research Center AN ASYNCHRONOUS DIVIDER IMPLEMENTATION Navaneeth Jamadagni and Jo Ebergen

2 Asynchronous Research Center Acknowledgements • Oracle Labs • DARPA • Asynchronous Research Center • Reviewers

3 Asynchronous Research Center Take Away • Division Algorithm • Usually retires 1 quotient digit per iteration • Sometimes retires 2 quotient digits per iteration • An Asynchronous Design • Exploits the time disparity between addition and shift operations • Result • Improvement in speed

4 Asynchronous Research Center Outline • Introduction • Divine Division • Hardware Design • Results • Conclusion

5 Asynchronous Research Center Outline • Introduction • Divine Division • Hardware Design • Results • Conclusion

6 Asynchronous Research Center Division Numerator, N = ((Quotient, Q) * (Denominator, D)) + Remainder, R

7 Asynchronous Research Center Long Division, Example 2 5 15 375 – 30 75 – 75 0

8 Asynchronous Research Center Long Division • Given a Numerator and a Denominator 1. Guess the quotient digit Ten choices, from the set {0 … 9} a. Iteration 2. Multiply the denominator by your guess 3. Subtract the product from the remainder to get a new remainder 4. Retire that quotient digit 5. Repeat steps 1 to 4 until the remainder is 0 or you run out of time

9 Asynchronous Research Center Two Division Methods Multiplicative Methods • Many choices (e.g., {0 …. 2 8 }) • Expensive multiplication • Retires many quotient bits per iteration • Few iterations • Digit-Recurrence Methods • Very few choices (e.g., {0,1} or {-2, -1, 0, 1, 2}) • Inexpensive multiplication • Retires one or two quotient bits per iteration • Many iterations •

10 Asynchronous Research Center SRT Division • Most common implementation in microprocessors • Carry-Save Additions or Subtractions • Guess by Carry Propagate Addition • Guess by Table Lookup • After Sweeney, Robertson and Tocher

11 Asynchronous Research Center SRT Division, Iteration Guess : quotient digit from the set { – 1, 0, 1} 1. Multiply : – 1 × D, 0 × D, 1 × D 2.

12 Asynchronous Research Center SRT Division, Iteration Guess : quotient digit from the set { – 1, 0, 1} 1. Multiply : – 1 × D, 0 × D, 1 × D 2. Subtract or Add: 3. CSA CSA = Carry Save Addition

13 Asynchronous Research Center SRT Division, Iteration Guess : quotient digit from the set { – 1, 0, 1} 1. Multiply : – 1 × D, 0 × D, 1 × D 2. Subtract or Add: 3. Table CSA Lookup or CPA = Carry Propagate Addition CPA

14 Asynchronous Research Center SRT Division, Iteration Guess : quotient digit from the set { – 1, 0, 1} 1. Multiply : – 1 × D, 0 × D, 1 × D 2. Subtract or Add : 3. CSA Basis for the Guess CPA = Carry Propagate Addition CSA = Carry Save Addition Retire : One quotient digit always 4.

15 Asynchronous Research Center Outline • Introduction • Divine Division • Hardware Design • Results • Conclusion

16 Asynchronous Research Center Divine Division “Divine” = Discover by guess work or Intuition • Carry-Save Addition or Subtraction only • Two versions in the paper: E and H • Developed at Sun Labs, by Jo Ebergen, Ivan Sutherland and Danny Cohen

17 Asynchronous Research Center Divine Division, Iteration Guess : quotient digit from the set {-2, -1, 0, 1, 2} 1. Multiply : – 2 × D, -1 × D, 0 × D, 1 × D, 2 × D 2.

18 Asynchronous Research Center Divine Division, Iteration Guess : quotient digit from the set {-2, -1, 0, 1, 2} 1. Multiply : – 2 × D, -1 × D, 0 × D, 1 × D, 2 × D 2. Subtract or Add : 3. CSA

19 Asynchronous Research Center Divine Division, Iteration Guess : quotient digit from the set {-2, -1, 0, 1, 2} 1. Multiply : – 2 × D, -1 × D, 0 × D, 1 × D, 2 × D 2. Subtract or Add : 3. 2 MSBs CSA

20 Asynchronous Research Center Divine Division, Iteration Guess : quotient digit from the set {-2, -1, 0, 1, 2} 1. Multiply : – 2 × D, -1 × D, 0 × D, 1 × D, 2 × D 2. Subtract or Add : 3. Parity Bits CSA Majority Bits

21 Asynchronous Research Center Divine Division, Iteration Guess : quotient digit from the set {-2, -1, 0, 1, 2} 1. Multiply : – 2 × D, -1 × D, 0 × D, 1 × D, 2 × D 2. Subtract or Add : 3. Parity Bits CSA Majority Bits Retire : One quotient digit usually, 1. Two quotient digits sometimes One more iteration than SRT for equal accuracy 2.

Asynchronous Research Center 22 Divine Division Choices 4 Value of the Remainder = Parity + Majority SUB2 3 & 2X* SUB1 SUB1 2 & & 2X* 2X* 1 2X* 2X 2X* 0 4X* 4X* 4X* 4X* -1 2X* 2X 2X* ADD1 ADD1 -2 & & 2X* 2X* ADD2 -3 & 2X* -4

Asynchronous Research Center 23 Divine Division Choices 4 Value of the Remainder = Parity + Majority SUB2 3 & 2X* SUB1 SUB1 2 & & 2X* 2X* 1 2X* 2X 2X* 0 4X* 4X* 4X* 4X* -1 2X* 2X 2X* ADD1 ADD1 -2 & & 2X* 2X* ADD2 -3 & 2X* -4

Asynchronous Research Center 24 Divine Division Choice: 4X* 4 Value of the Remainder = Parity + Majority SUB2 3 & 2X* SUB1 SUB1 2 & & Quotient = 2X* 2X* 0 and 0 1 2X* 2X 2X* Remainder = 0 4X* 4X* 4X* 4X* Left shift by 2 -1 2X* 2X 2X* and Invert MSBs ADD1 ADD1 -2 & & 2X* 2X* ADD2 -3 & 2X* -4

Asynchronous Research Center 25 Divine Division Choice: 2X* 4 Value of the Remainder = Parity + Majority SUB2 3 & 2X* SUB1 SUB1 2 & & Quotient = 2X* 2X* 0 1 2X* 2X 2X* Remainder = 0 4X* 4X* 4X* 4X* Left shift by 1 -1 2X* 2X 2X* and Invert MSBs ADD1 ADD1 -2 & & 2X* 2X* ADD2 -3 & 2X* -4

Asynchronous Research Center 26 Divine Division Choice: 2X 4 Value of the Remainder = Parity + Majority SUB2 3 & 2X* SUB1 SUB1 2 & & Quotient = 2X* 2X* 0 1 2X* 2X 2X* Remainder = 0 4X* 4X* 4X* 4X* Left shift by 1 -1 2X* 2X 2X* ADD1 ADD1 -2 & & 2X* 2X* ADD2 -3 & 2X* -4

Asynchronous Research Center 27 Divine Division Choice: SUB1 & 2X* 4 Value of the Remainder = Parity + Majority SUB2 3 & 2X* SUB1 SUB1 2 & & Quotient = 2X* 2X* 1 1 2X* 2X 2X* Remainder = 0 4X* 4X* 4X* 4X* SUB 1 × D -1 2X* 2X 2X* & Left shift by 1 ADD1 ADD1 -2 & & and 2X* 2X* Invert MSBs ADD2 -3 & 2X* -4

Asynchronous Research Center 28 Divine Division Choice: SUB2 & 2X* 4 Value of the Remainder = Parity + Majority SUB2 3 & 2X* SUB1 SUB1 2 & & Quotient = 2X* 2X* 2 1 2X* 2X 2X* Remainder = 0 4X* 4X* 4X* 4X* SUB 2 × D -1 2X* 2X 2X* & Left shift by 1 ADD1 ADD1 -2 & & and 2X* 2X* Invert MSBs ADD2 -3 & 2X* -4

Asynchronous Research Center 29 Divine Division Choice: ADD1 & 2X* 4 Value of the Remainder = Parity + Majority SUB2 3 & 2X* SUB1 SUB1 2 & & Quotient = 2X* 2X* -1 1 2X* 2X 2X* Remainder = 0 4X* 4X* 4X* 4X* ADD 1 × D -1 2X* 2X 2X* & Left shift by 1 ADD1 ADD1 -2 & & and 2X* 2X* Invert MSBs ADD2 -3 & 2X* -4

Asynchronous Research Center 30 Divine Division Choice: ADD2 & 2X* 4 Value of the Remainder = Parity + Majority SUB2 3 & 2X* SUB1 SUB1 2 & & Quotient = 2X* 2X* -2 1 2X* 2X 2X* Remainder = 0 4X* 4X* 4X* 4X* ADD 2 × D -1 2X* 2X 2X* & Left shift by 1 ADD1 ADD1 -2 & & and 2X* 2X* Invert MSBs ADD2 -3 & 2X* -4

31 Asynchronous Research Center Number of Iterations per Division • One million pairs of uniform-random 25-bit input operands 1 0,9 Average = 22.6 0,8 Probability 0,7 Divine Division SRT Division 0,6 0,5 0,4 0,3 0,2 0,1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Number of Iterations per division (25-bit operands)

32 Asynchronous Research Center Outline • Introduction • Divine Division • Hardware Design • Results • Conclusion

33 Asynchronous Research Center Asynchronous Divine Divider • Control Path • Uses GasP modules • Generates the control signals for the registers • Delay matched to data path • Shift steps are faster than addition steps • Asynchronous loop counter • Data Path • Registers and computational blocks (e.g., CSA) • Single rail bundled data

Asynchronous Research Center 34 Data Path 1. Guess the first Quotient Digit

Asynchronous Research Center 35 Data Path 2. Carry Save Add 3. Retires one digit 4. Guess the next quotient digit

Asynchronous Research Center 36 Data Path 2. Left shift by 1 3. Retires 1 quotient digit, namely 0 4. Guess the next quotient digit

Asynchronous Research Center 37 Data Path 2. Left shift by 2 3. Retires 2 quotient digits, 0 and 0 4. Guess the next quotient digit

38 Asynchronous Research Center Outline • Introduction • Divine Division • Hardware Design • Results • Conclusion