Reliability Enhancement via Sleep Transistors Frank Sill Torres + , - PowerPoint PPT Presentation

Reliability Enhancement via Sleep Transistors Frank Sill Torres + , Claas Cornelius*, Dirk Timmermann* + Department of Electronic Engineering, Federal University of Minas Gerais, Belo Horizonte, Brazil * Inst. of Applied Microelectronics and Computer Engineering, University of Rostock, Germany

Focus / Main ideas 1. Approach for extension of expected lifetime 2. Application of simulation environment for MTTF estimation Sill Torres et al.– Reliability w/ Sleep Transistors 2

Outline  Motivation  Preliminaries  Reliability Enhancement via Sleep Transistors  Simulation Environment  Results  Conclusion Sill Torres et al.– Reliability w/ Sleep Transistors 3

Motivation Technology Development Gulftown 1.170 Mil. 1200 1200 140 nm # Transistors (Mill.) 120 nm 130 nm 900 900 100 nm Tecnology Tecnologia Wolfdale 80 nm 90 nm 45 nm 65 nm 410 Mil. 600 600 60 nm Yonah Prescott 32 nm 151 Mil. 125 Mil. Northwood 40 nm 300 300 55 Mil. Wolfdale 20 nm 410 Mil. 0 0 nm 2002 2002 2004 2004 2006 2006 2008 2008 2010 2010 Year Ano Probability for failures increases due to:  Increasing transistor count  Shrinking technology Sill Torres et al.– Reliability w/ Sleep Transistors 4

Motivation Error classification Error Temporary Permanent Soft errors, Voltage drop, Coupling, … Reduced Performance Malfunction Process variations, Electro- Electromigration, migration, Oxide wearout, Oxide breakdown ... NBTI, ... Sill Torres et al.– Reliability w/ Sleep Transistors 5

Preliminaries Power-Gating with Sleep Transistors  Very well-known and effective Sleep approach for leakage reduction virtual VDD  Insertion of sleep transistors (mostly with high-threshold voltage) between logic module High-V th Logic block and supply  Disconnection from supply virtual GND during standby Sleep M. Powell, et al., Proc. ISLPED , 2000. A. Ramalingam, et al., Proc. ASP-DAC , 2005. Sill Torres et al.– Reliability w/ Sleep Transistors 6

Preliminaries Time Dependent Failure Mechanisms  Electromigration (EM) – Performance reduction and errors – Depending on currents and temperature  Negative Bias Temperature Instability (NBTI) – Performance reduction – Depending on voltage level and temperature  Time Dependent Dielectric Breakdown (TDDB) – Performance reduction and errors – Depending on voltage level and temperature Increase of lifetime through reduction of supply voltage and activity Sill Torres et al.– Reliability w/ Sleep Transistors 7

Reliability Enhancement via Sleep Transistors Concept and Realization  Basic idea: Reduction of degradation via module deactivation Module Module t life-new ≈ t life-old + t off Sill Torres et al.– Reliability w/ Sleep Transistors 8

Reliability Enhancement via Sleep Transistors Concept and Realization  Basic idea: Reduction of degradation via module deactivation  Problem: What to do at run-time ? Module 1 Instance 1 t life-system = t life-module ≈ t life-old + t off ≈ 2* t life-old + t sleep Module 1 Instance 2 Sill Torres et al.– Reliability w/ Sleep Transistors 9

Reliability Enhancement via Sleep Transistors Concept and Realization  Basic idea: Reduction of degradation via module deactivation  Problem: What to do at run-time ? Module 1 Instance 1 Module 2 SLEEP Module 1 MUX Instance 2 Sill Torres et al.– Reliability w/ Sleep Transistors 10

Reliability Enhancement via Sleep Transistors Expectations  Lifetime – Increase by more than factor 2 (not linear relation between effective voltage and failure mechanisms)  Area – Increase by slightly more than factor 2 – Ca. 50 % less than Triple Modular Redundancy (TMR)  Power dissipation – Slight increase of dynamic power dissipation – Increase of leakage by ca. factor 2  Delay – Slight increase through multiplexer delays Sill Torres et al.– Reliability w/ Sleep Transistors 11

Reliability Enhancement via Sleep Transistors Comments  Application – Limited improvements for devices with long standby times (mobiles, home PCs) – High improvements for high availability applications (server, aerospace equipment, mobile communication nodes)  Multiplexer – Problem: no deactivation of multiplexer – Solution: use of transmission gates (less vulnerable)  Control signals (for sleep transistor, multiplexer) – Logic for control signal generation must be reliable too – Hence: reliable implementation (HighTox, wire widening, …) – More research required Sill Torres et al.– Reliability w/ Sleep Transistors 12

Simulation Environment  Desired: Simulative estimation of average time until first failure (also known as Mean Time To Failure – MTTF)  Solution: – Application of voltage controlled variable elements and parameters for failure modeling (xSpice, VerilogA, …) – Linear increase/decrease of control voltage at simulation time  Example: HSPICE model of transistor with TDDB and varying width V0 Vref 0 DC 1 V1 Vctrl 0 PULSE 1e12 0 0 1E-2 1E-9 1E1 2E1 M0 D G N1 0 nmos W='1e-7 * V(Vctrl)/V(Vref)' M1 N1 G S 0 nmos W='1e-7 * V(Vctrl)/V(Vref)' G1 G N1 VCR Vctrl 0 10 Sill Torres et al.– Reliability w/ Sleep Transistors 13

Results Mean Time To Failure (MTTF) 2.2 ( BPTM 22nm, 100 samples, TDDB and EM modeling, basic MTTF of 300 clock cycles, relaxed timing, w/o temperature consideration ) Sill Torres et al.– Reliability w/ Sleep Transistors 14

Results Delay / Power / Area Average values: Delay: + 7 %, Power: + 5 %, Area: + 110 % Sill Torres et al.– Reliability w/ Sleep Transistors 15

Conclusion  Progressing susceptibility of current technologies against severe failure mechanisms  Extension of expected lifetime by alternating (de-)activation of redundant blocks via sleep transistors  Environment for simulation of time-dependent degradation of design components  Increase of MTTF by more than factor 2 through proposed approach  Factor 1.2 for relation of average increase of MTTF and area  Future tasks: – Application of selective redundancy techniques – Merging with approaches on system level – Analysis of control logic Sill Torres et al.– Reliability w/ Sleep Transistors 16

Thank you! franksill@ufmg.br claas.cornelius@uni-rostock.de Sill Torres et al.– Reliability w/ Sleep Transistors 17

Motivation Time-Dependent Dielectric Breakdown (TDDB)  Tunneling currents Wear out of gate oxide  Creation of conducting path between Gate and Substrate, Drain, Source  Depending on electrical field over gate oxide, temperature (exp.) , Source: Pey&Tung and gate oxide thickness (exp.)  Also: abrupt damage due to extreme overvoltage (e.g. Electro- Static Discharge) Source: Pey&Tung Sill Torres et al.– Reliability w/ Sleep Transistors 18

Reliability Enhancement via Sleep Transistors Realization Sill Torres et al.– Reliability w/ Sleep Transistors 19

Reliability Enhancement via Sleep Transistors Blocks / Requirements Sill Torres et al.– Reliability w/ Sleep Transistors 20

Simulation Environment Overview Sill Torres et al.– Reliability w/ Sleep Transistors 21

Simulation Environment Error Modeling Sill Torres et al.– Reliability w/ Sleep Transistors 22