PATMOS 2010 An On-Chip Flip-flop Characterization Circuit Andrea Veggetti (ST Agrate) Abhishek Jain (ST Noida) Dennis Crippa (ST Agrate) Pier Luigi Rolandi (ST Agrate)
Agenda • Motivation • Flip-flop Characterization Parameters • Proposed Solution (Flip-flop Characterization Circuit) • Modes of Operation • CAD Results • Silicon Results • Conclusions 2
Motivation • Flip-flops -> Vital Component in Sequential Circuits. Their Performance determines the performance of circuit. • To observe the Correlation between CAD signoff and actual values on Silicon. • Accurate Measurements of pico-second order delays can only be done by On-Chip methods. • With technology advancements flip-flops circuits are getting more and more complex with more features. Need to validate their performance on Silicon. 3
Flip-flop Characterization Parameters • Power Parameters • Timing Parameters – Static Power – Setup Time - Under different configurations – Hold Time – Dynamic Power – Clock to Output Delay - With Different Data Activity Rates 4
Proposed Solution Flip-flop Characterization Circuit (FCC) • Single On-chip mesurement system for both timing and power characterization. • Consists of optional digital Controller and Characterization circuit. • Characterization unit could be programmed to operate in different configurations – Oscillator for Timing Characterization – Shift Register for Power Characterization. • Timing values are extracted from difference of period of oscillations of oscillator in different configurations. • Power characterization is done at dedicated power supply for DUT. 5
Proposed Solution (Contd.) • Data and Clock path could • Clock and Data Path Delay programmed using muxes. units are based upon delay • Multiple stages to be repeated cells with very small delay to have accurate mesurement difference of pico-seconds and resolution. order. • Two different power domains for accurate power • Alternate stage of Basecell mesurement. consists of alternate polarity to – Default (for complete Circuit) minimize rise-fall error. – Vddff (for DUT) 6
Oscillator Configuration Timing Parameter Characterization 7
Shifter Configuration Power Parameter Characterization Different Power Supply Domain vddff • External Data and Clock applied to flip-flop. • Dedicated Power supply for flip-flop under test. • Dynamic Measurement:- • Power measurements are performed for different data activity rates. • Static Measurment:- • Power measurements are performed for different Data, Clock and Output configuration. 8
CAD Results: Timing Parameters • Simulation Setup:- TCP-Q (Measured) TCP-Q (Actual) TCP-Q (Measured) TCP-Q (Actual) 180 180 • CMOS 40nm Technology Node • Synopsys XA simulator 130 130 • 100 Stage Characterization 80 Circuit 80 • DUT: Master Slave D Flip-flop 30 30 based upon C 2 MOS Tristate CP – D Delay Latches -50 0 50 100 150 200 -20 -50 0 50 100 150 200 -20 • Simulation Corner: Clock-to-Delay(ps) Vs Clock-Data Path Delay(ps) for Setup Time Estimation TYP_1.0V_25C. TCP-Q (Measured) TCP-Q (Actual) TCP-Q (Measured) TCP-Q (Actual) 200 200 • Timing Parameter 150 150 Characterization: 100 100 • Hold Time: 5ps 50 • Setup Time: 70ps 50 • CLK to Q Delay: 132ps 0 0 -80.00 -60.00 -40.00 -20.00 0.00 20.00 40.00 60.00 -80.00 -60.00 -40.00 -20.00 0.00 20.00 40.00 60.00 CP – D Delay -50 -50 • Sources of Error: Clock-to-Delay(ps) Vs Clock-Data Path Delay(ps) for Hold Time Estimation • 8-10ps due to different path 9 delays of MUX
CAD Results: Power Parameters 9.00E-06 9.00E-06 DUT Power DUT Power 8.00E-06 8.00E-06 7.00E-06 7.00E-06 6.00E-06 6.00E-06 5.00E-06 5.00E-06 4.00E-06 4.00E-06 3.00E-06 3.00E-06 2.00E-06 2.00E-06 1.00E-06 1.00E-06 0.00E+00 0.00E+00 50% 33% 25% 20% 17% 14% 13% 11% 10% 50% 33% 25% 20% 17% 14% 13% 11% 10% Power Dynamic Current in amps through hundred DUT stages Vs Data Measurements Activity Rate w.r.t. to Clock at 1V, 25C and 10MHz Clock Frequency Performed On 1.40E-05 DUT power DUT Power 1.40E-05 DUT Power 1.20E-05 supply VDDFF 1.20E-05 1.00E-05 1.00E-05 8.00E-06 8.00E-06 6.00E-06 6.00E-06 4.00E-06 4.00E-06 2.00E-06 2.00E-06 0.00E+00 0.00E+00 0.9V 1.0V 1.2V 0.9V 1.0V 1.2V Leakage Current in amps through hundred DUT stages Vs Applied Voltage at 150C 10
Silicon Results CP-Q Rise Arc Silicon CP-Q Fall Arc Silicon CP-Q Rise Arc CAD CP-Q Fall Arc CAD CP-Q Rise Arc Silicon CP-Q Fall Arc Silicon CP-Q Rise Arc CAD CP-Q Fall Arc CAD 3.00E-10 Fourtune Memory Cuts Fourtune Memory Cuts 3.00E-10 Fourtune ALLCELL Fourtune ALLCELL Fourtune Memory Cuts Fourtune Memory Cuts BISC for Access Time BISC for Access Time Fourtune ALLCELL Fourtune ALLCELL structures structures Characterization Characterization BISC for Access Time BISC for Access Time 2.50E-10 structures structures Characterization Characterization 2.50E-10 2.00E-10 Low Power Block 2 Low Power Block 2 2.00E-10 Low Power Block 2 Low Power Block 2 1.50E-10 MERCURY_C40LP MERCURY_C40LP 1.50E-10 MERCURY_C40LP MERCURY_C40LP 3mm X 3mm 3mm X 3mm 3mm X 3mm 3mm X 3mm 1.00E-10 Low Power Block 1 Low Power Block 1 1.00E-10 Low Power Block 1 Low Power Block 1 5.00E-11 Ring Oscillator Ring Oscillator 5.00E-11 Structures Structures Ring Oscillator Ring Oscillator Structures Structures 0.00E+00 Ultra Low Voltage IPs Ultra Low Voltage IPs 0.00E+00 Ultra Low Voltage IPs Ultra Low Voltage IPs T=-40.00 T=-40.00 T=-40.00 T=25.00 T=25.00 T=25.00 T=125.00 T=125.00 T=125.00 T=-40.00 T=-40.00 T=-40.00 T=25.00 T=25.00 T=25.00 T=125.00 T=125.00 T=125.00 V=0.90 V=1.00 V=1.10 V=0.90 V=1.00 V=1.10 V=0.90 V=1.00 V=1.10 V=0.90 V=1.00 V=1.10 V=0.90 V=1.00 V=1.10 V=0.90 V=1.00 V=1.10 CAD Vs Silicon Results for Clock-to-Q Delay (sec) Mercury_C40LP • 40nm Mercury Testchip in SAMSUNG CMOS process. • 100 stage Design implemented to measure Clock to Q delay. DUT: Master Slave D Flip-flop based upon C 2 MOS Tristate Latches • • 2% misalignment between CAD and Silicon at nominal voltage range. • 12% misalignment between CAD and Silicon at Lower Voltage. 11
Conclusions • Single system for complete characterization of flip-flop is presented. • The system gives high accuracy and high resolution. • Useful for SPICE model validation • Useful for Comparative Analysis of Different flip-flop structures. • CAD analyisis shown for complete system shows good results and error under acceptable limits. • Sub-system to measure Clock to Q delay has been proven on silicon. • Complete system to be validated on silicon. • System could be used for different flip-flop types. • System could be improved further to do characterization at different load and slopes. 12
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