Systems Timing Sequential Circuits Shankar Balachandran* Associate - PowerPoint PPT Presentation

Spring 2015 Week 6 Module 33 Digital Circuits and Systems Timing Sequential Circuits Shankar Balachandran* Associate Professor, CSE Department Indian Institute of Technology Madras *Currently a Visiting Professor at IIT Bombay

Sequential Circuit Timing Once the functionality of a sequential network is designed, its timing parameters must be determined. Timing problems can be very subtle because timing parameters can vary with device age and other operating conditions. Analysis and Design of Sequential Logic Circuits 2

Timing Parameters  Global setup time ( T su )  Global hold time ( T h )  Maximum clock frequency  Clock skew. These parameters are derived using the circuit (known) delays described below. t io – delay from input of IFL to output of OFL t if – delay from circuit inputs of flip-flop inputs t fo – delay from flip-flop outputs to circuit outputs t ff – delay from flip-flop outputs to flip-flop inputs t c-q – clock to Q propagation delay of flip-flops t su – setup time of flip-flops t h – hold time of flip-flops t c – clock delay; time required for clock to reach all flip-flops Analysis and Design of Sequential Logic Circuits 3

Global Setup and Hold Times  Changes that occur at inputs can be delayed by as much as maximum t if by the time they reach the flip-flop inputs. Hence, we want to setup circuit inputs relative to clock edge appearing at the flip-flops. T h T su CLK (at clock source) t c t h CK (at FF clock input) X (at sequential circuit input) t if t su t if D (at FF input)    T t t t s u su if c max max min  Similarly, hold time of the circuit inputs relative to the system clock at the source is given by    T t t t h h if c max min max Analysis and Design of Sequential Logic Circuits 4

Maximum Clock Frequency Q j D j CK i Λ Comb. CK j Q i logic t su t ff D i Q i t C-Q Λ D j CK i T ck (= T clk ) t ff CLK Edge Triggering  For an edge-triggered circuit: minimum clock period is,    T t t t clk  C Q ff su max max max  Maximum Clock Frequency: 1  f clk T clk Analysis and Design of Sequential Logic Circuits 5

Timing Violations    T t t t  c k l C Q f f s u max max max  The clock period ( T clk ) has a lower bound of t ff.max .  If the clock period is equal to ( t ff.max + t C-Q.max ) then the flip-flop state changes can violate setup times.  Remedy :  Use faster flip-flops (decrease t C-Q )  Use faster gates (decrease t ff )  Use a slower clock (increase clock period, T clk ) Analysis and Design of Sequential Logic Circuits 6

Clock Skew  The previous discussion assumes that clock signals arrive at all flip-flops simultaneously - this is not a good assumption since it is not true in practice.  Because of different wire lengths over which the clock signals travel and the load at the destination, there is a slight difference in clock arrival times at different flip-flop inputs.  Clock skew, t skew , is the difference in time between triggering edges seen at different flip-flops. Clock skew affects minimum T clk . Analysis and Design of Sequential Logic Circuits 7

Max. Clock Frequency with Skew t skew CK i Q j D j t C-Q Λ Comb. CK j CK j logic D i Q i t skew Q j t ff t su Λ CK i t ff D i CLK T ck (= T clk )  Therefore, for an edge-triggered circuit with clock skew,     T t t t t  clk skew C Q ff su max max max max  Clock skew is a significant factor in determining the speed of high- performance synchronous circuits. The larger the skew, the slower the circuit will operate. Analysis and Design of Sequential Logic Circuits 8

Timing Analysis Example For the circuit given below determine all the sequential circuit timing parameters. For a D flip-flop use: t su = 2ns, t h = 15ns and t C-Q = 20ns For a NAND gate use: t p,max = 10ns and t p,min = 3ns Analysis and Design of Sequential Logic Circuits 10

  t 3 t 30 ns if , max p , max, nand   t 2 t 6 ns if , min p , min, nand .   t 2 t 20 ns ff , max p , max, nand   t 2 t 6 ns ff , min p , min, nand   t 2 t 20 ns For a D flip-flop use: t su = 2ns, t h = 15ns, t C-Q = 20ns c , max p , max, nand For a NAND gate use: t p,max = 10ns, t p,min = 3ns   t 2 t 6 ns c , min p , min, nand        T t t t 2 30 6 26 ns su su ,max if ,max c ,min        T t t t 20 15 6 29 ns h h ,max if ,min c ,max        T t t t 20 20 2 42 ns  clk C Q ,max ff ,max su ,max   f 1/ 42 ns 23.8 MHz clk ,max Analysis and Design of Sequential Logic Circuits 11

Sequential Systems Using Latches Latches can be used to create sequential systems. However, since these  are level-triggered clocking must be done carefully – must ensure that state changes only once per clock cycle. t w < t ff.min + t D-Q.min Q j D j Comb. CLK CK j logic D i Q i > ( t D-Q.max + t ff.max + t su.max ) CK i t ff CLK Use narrow-width clock whose pulse width is less than the fastest possible path  through the combinational logic . To guarantee correct next state, make sure that the clock period is longer than the  worst-case propagation delay through the combinational logic. Analysis and Design of Sequential Logic Circuits 12

Clocking Frequency with Latches T clk CK i t skew t w Q j D j CK t su j Comb. CK j D j logic t D-Q D i Q i t skew CK i Q t ff t su t ff j CLK D i         T t t t t t t  clk skew w su D Q ff su max min max max max Analysis and Design of Sequential Logic Circuits 14

End of Week 6: Module 33 Thank You Intro to State Machines 15