IEEE 1149.1 JTAG Boundary Scan Standard Shaahin Hessabi Department of Computer Engineering Sharif University of Technology Adapted, with modifications, from lecture notes prepared by the book authors Slide 1 of 36
Outline Bed-of-nails tester Motivation for boundary scan standard System view of boundary scan hardware Elementary scan cell Test Access Port (TAP) controller Boundary scan instructions Summary Sharif University of Technology Slide 2 of 36 Lecture 28: Boundary Scan
Bed-of-Nails Tester Concept Sharif University of Technology Slide 3 of 36 Lecture 28: Boundary Scan
Bed-of-Nails Tester Sharif University of Technology Slide 4 of 36 Lecture 28: Boundary Scan
Motivation for Standard Bed-of-nails printed circuit board tester gone We put components on both sides of PCB & replaced DIPs with flat packs to reduce inductance Nails would hit components Reduced spacing between PCB wires Nails would short the wires PCB Tester must be replaced with built-in test delivery system -- JTAG does that Need standard System Test Port and Bus Integrate components from different vendors One chip has test hardware for other chips Test bus identical for various components Sharif University of Technology Slide 5 of 36 Lecture 28: Boundary Scan
Purpose of Standard Lets test instructions and test data be serially fed into a CUT Allows reading out test results Allows RUNBIST command as an instruction Too many shifts to shift in external tests JTAG can operate at chip, PCB, & system levels Allows control of tri-state signals during testing Lets other chips collect responses from CUT Lets system interconnect be tested separately from components Lets components be tested separately from wires Sharif University of Technology Slide 6 of 36 Lecture 28: Boundary Scan
System Test Logic Sharif University of Technology Slide 7 of 36 Lecture 28: Boundary Scan
Instruction Register Loading with JTAG Sharif University of Technology Slide 8 of 36 Lecture 28: Boundary Scan
System View of Interconnect Sharif University of Technology Slide 9 of 36 Lecture 28: Boundary Scan
Boundary Scan Chain View Sharif University of Technology Slide 10 of 36 Lecture 28: Boundary Scan
Elementary Boundary Scan Cell Normal mode: 1. Mode-control = 0 Scan mode: Shift DR = 1 2. First scan FF is driven by TDI, Last scan FF drives TDO Capture mode: Shift DR = 0 3. Update mode: Mode-control = 1 4. Sharif University of Technology Slide 11 of 36 Lecture 28: Boundary Scan
Serial Board / MCM Scan Sharif University of Technology Slide 12 of 36 Lecture 28: Boundary Scan
Parallel Board / MCM Scan Sharif University of Technology Slide 13 of 36 Lecture 28: Boundary Scan
Independent Path Board / MCM Scan Sharif University of Technology Slide 14 of 36 Lecture 28: Boundary Scan
Tap Controller Signals Test Access Port (TAP) includes these signals: Test Clock Input ( TCK ) -- Clock for test logic Can run at different rate from system clock Test Mode Select ( TMS ) -- Switches system from functional to test mode Test Data Input ( TDI ) -- Accepts serial test data and instructions -- used to shift in vectors or one of many test instructions Test Data Output ( TDO ) -- Serially shifts out test results captured in boundary scan chain (or device ID or other internal registers) Test Reset ( TRST ) -- Optional asynchronous TAP controller reset Sharif University of Technology Slide 15 of 36 Lecture 28: Boundary Scan
Tap Controller State Diagram Sharif University of Technology Slide 16 of 36 Lecture 28: Boundary Scan
States of TAP Controller Test-Logic-Reset: normal mode Run-Test/Idle: wait for internal test such as BIST Select-DR-Scan: initiate a data-scan sequence Capture-DR: load test data in parallel Shift-DR: load test data in series Exit1-DR: finish phase-1 shifting of data Pause-DR: temporarily hold the scan operation (e.g., allow the bus master to reload data) Exit2-DR: finish phase-2 shifting of data Update-DR: parallel load from associated shift registers Note: Controls for IR are similar to those for DR. Sharif University of Technology Slide 17 of 36 Lecture 28: Boundary Scan
Tap Controller Timing Sharif University of Technology Slide 18 of 36 Lecture 28: Boundary Scan
TAP Controller Power-Up Reset Logic Sharif University of Technology Slide 19 of 36 Lecture 28: Boundary Scan
Boundary Scan Instructions Slide 20 of 36
Major Modes of Operation Non-invasive mode: standard provides resources guaranteed to be independent of system logic These resources enable asynchronous communication with the outside world (serially read in test data and instructions or serially read out test results) Activities are invisible to the normal IC behavior Pin-permission modes: takes control of the IC I/O pins, thus disconnecting the system logic from the outside world. Allow testing of the system interconnect separately from component testing, and also allow testing of components separately from system interconnect testing. The testing activities totally disrupt the normal IC behavior. Sharif University of Technology Slide 21 of 36 Lecture 28: Boundary Scan
SAMPLE / PRELOAD Instruction-- SAMPLE Purpose: Get snapshot of normal chip output signals 1. Put data on boundary scan chain before next instruction 2. Sharif University of Technology Slide 22 of 36 Lecture 28: Boundary Scan
SAMPLE / PRELOAD Instruction -- PRELOAD Sharif University of Technology Slide 23 of 36 Lecture 28: Boundary Scan
EXTEST Instruction Purpose: Test off-chip circuits and board-level interconnections Sharif University of Technology Slide 24 of 36 Lecture 28: Boundary Scan
Execution of EXTEST Instruction Phase 1: Shift-DR (Chip1) Phase 2: Update-DR (Chip1) Capture-DR (Chip2) Phase 3: Shift-DR (Chip2) Sharif University of Technology Slide 25 of 36 Lecture 28: Boundary Scan
Execution of INTEST Instruction Purpose: 1. Shifts external test patterns onto component 2. External tester shifts component responses out Phase 1: Shift-DR Phase 2: Update-DR Sharif University of Technology Slide 26 of 36 Lecture 28: Boundary Scan
Execution of INTEST Instruction (cont’d) Phase 3: Capture-DR Phase 4: Shift-DR Sharif University of Technology Slide 27 of 36 Lecture 28: Boundary Scan
RUNBIST Instruction Purpose: Allows you to issue BIST command to component through JTAG hardware Optional instruction Lets test logic control state of output pins 1. Can be determined by pin boundary scan cell 2. Can be forced into high impedance state BIST result (success or failure) can be left in boundary scan cell or internal cell Shift out through boundary scan chain May leave chip pins in an indeterminate state (reset required before normal operation resumes) Sharif University of Technology Slide 28 of 36 Lecture 28: Boundary Scan
CLAMP Instruction Purpose: Forces component output signals to be driven by boundary-scan register Bypasses the boundary scan chain by using the one-bit Bypass Register Optional instruction May have to add RESET hardware to control on-chip logic so that it does not get damaged (by shorting 0’s and 1’s onto an internal bus, etc.) Sharif University of Technology Slide 29 of 36 Lecture 28: Boundary Scan
IDCODE Instruction Purpose: Connects the component device identification register serially between TDI and TDO In the Shift-DR TAP controller state Allows board-level test controller or external tester to read out component ID Required whenever a JEDEC identification register is included in the design Sharif University of Technology Slide 30 of 36 Lecture 28: Boundary Scan
Device ID Register --JEDEC Code MSB LSB 31 28 27 12 11 1 0 Part Manufacturer ‘1’ Version Number Identity (4 bits) (16 bits) (11 bits) (1 bit) Sharif University of Technology Slide 31 of 36 Lecture 28: Boundary Scan
USERCODE Instruction Purpose: Intended for user-programmable components (FPGA’s, EEPROMs, etc.) Allows external tester to determine user programming of component Selects the device identification register as serially connected between TDI and TDO User-programmable ID code loaded into device identification register On rising TCK edge Required when Device ID register included on user-programmable component Sharif University of Technology Slide 32 of 36 Lecture 28: Boundary Scan
HIGHZ Instruction Purpose: Puts all component output pin signals into high- impedance state Control chip logic to avoid damage in this mode May have to reset component after HIGHZ runs Optional instruction Sharif University of Technology Slide 33 of 36 Lecture 28: Boundary Scan
BYPASS Instruction Purpose: Bypasses scan chain with 1-bit register Sharif University of Technology Slide 34 of 36 Lecture 28: Boundary Scan
Optional / Required Instructions Instruction Status BYPASS Mandatory CLAMP Optional EXTEST Mandatory HIGHZ Optional IDCODE Optional INTEST Optional RUNBIST Optional SAMPLE / PRELOAD Mandatory USERCODE Optional Sharif University of Technology Slide 35 of 36 Lecture 28: Boundary Scan
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