mips datapath
play

MIPS Datapath CMSC 301 Prof Szajda Goal Build an architecture to - PowerPoint PPT Presentation

Oct 07, 2023 •275 likes •1.27k views

MIPS Datapath CMSC 301 Prof Szajda Goal Build an architecture to support the following instructions w Arithmetic: add, sub, addi, slt w Memory references: lw, sw w Branches: j, beq Process 1) Design basic framework that is needed by all

  1. MIPS Datapath CMSC 301 Prof Szajda

  2. Goal • Build an architecture to support the following instructions w Arithmetic: add, sub, addi, slt w Memory references: lw, sw w Branches: j, beq

  3. Process 1) Design basic framework that is needed by all instructions 2) Build a computer for each operation individually 3) Add MUXs to choose between different operations 4) Add control signals to control the MUXs

  4. MIPS Steps • Get an instruction from memory using the Program Counter (PC) • Read one or two registers each instruction w One register: addi, lw w Two registers: add, sub, slt, sw, beq • All instructions use ALU after reading regs • Some instructions also access Memory • Write result to Register file

  5. Framework Get instruction from memory

  6. Framework Get Read instruction from from register memory file

  7. Framework Use ALU Get Read instruction from from register memory file

  8. Framework Use ALU Get Read Access instruction from memory from register memory file

  9. Framework Use ALU Get Read Access instruction from memory from register memory file Write register file

  10. Get Instruction Where do we store instructions?

  11. Get Instruction Where do we store instructions? Memory Data Address Instruction Memory

  12. Get Instruction How do we know at what address to fetch instruction? Data Address Instruction Memory

  13. Get Instruction How do we know at what address to fetch instruction? Program Counter Program Counter Data (PC) Instruction Memory

  14. Get Instruction What do we end up with? Program Counter Data (PC) Instruction Memory

  15. Get Instruction What do we end up with? Instruction Program Counter Instruction (PC) Instruction Memory

  16. Get Instruction What happens to the PC each instruction? Program Counter Instruction (PC) Instruction Memory

  17. Get Instruction What happens to the PC each instruction? Increment by 4B 4 Program Counter Instruction (PC) Instruction Memory

  18. “Add” Instruction Use ALU Get Read instruction from from register memory file Write register file

  19. “Add” Instruction Operation rs rt rd shamt funct # meaning add 3 5 2 0 32 # $2 <- $3 + $5 4 Read Use ALU from register op/fun PC file Read Addr rs Out Data rt Instruction rd Inst Memory imm Write register file

  20. “Add” Instruction Operation rs rt rd shamt funct # meaning add 3 5 2 0 32 # $2 <- $3 + $5 How many registers do we need to read? 4 Use ALU op/fun PC Read Addr rs Out Data Instruction rt Register File rd Memory Inst imm Write register file

  21. “Add” Instruction Operation rs rt rd shamt funct # meaning add 3 5 2 0 32 # $2 <- $3 + $5 How many registers do we need to read? 2 4 Use ALU op/fun PC Read Addr rs Out Data Instruction rt Register File rd Memory Inst imm Write register file

  22. “Add” Instruction Operation rs rt rd shamt funct # meaning What part of add 3 5 2 0 32 # $2 <- $3 + $5 instruction tells us the register number? 4 Use ALU op/fun src1 src1data PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst imm Write register file

  23. “Add” Instruction Operation rs rt rd shamt funct # meaning What part of add 3 5 2 0 32 # $2 <- $3 + $5 instruction tells us the register number? 4 rs & rt Use ALU op/fun src1 src1data PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst imm Write register file

  24. “Add” Instruction Operation rs rt rd shamt funct # meaning add 3 5 2 0 32 # $2 <- $3 + $5 4 op/fun src1 src1data PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst imm Write register file

  25. “Add” Instruction Operation rs rt rd shamt funct # meaning add 3 5 2 0 32 # $2 <- $3 + $5 How do we know which 4 register to write? src1 src1data op/fun PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst imm destdata

  26. “Add” Instruction Operation rs rt rd shamt funct # meaning add 3 5 2 0 32 # $2 <- $3 + $5 How do we know which 4 register to write? src1 src1data op/fun rd PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst destreg imm destdata

  27. “Add” Instruction Operation rs rt rd shamt funct # meaning add 3 5 2 0 32 # $2 <- $3 + $5 4 src1 src1data op/fun PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst destreg imm destdata

  28. What happens if instruction reads and writes same register? Operation rs rt rd shamt funct # meaning add 3 5 3 0 32 # $3 <- $3 + $5 4 src1 src1data op/fun PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst destreg imm destdata

  29. What happens if instruction reads and writes same register? Operation rs rt rd shamt funct # meaning add 3 5 3 0 32 # $3 <- $3 + $5 What would happen if we allowed write to occur at any time? Clock is dependent on longest path (lw) 4 Quick operations may loop twice through machine, getting incorrect result. src1 src1data op/fun PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst destreg imm destdata

  30. Reading/Write Registers • When does register get written? w At the end of the clock cycle w Edge-triggered circuits

  31. “Addi” Instruction Operation rs rt imm # meaning What addi $5,$3,6 3 5 6 # $5 <- $3 + 6 registers do we read? 4 src1 src1data op/fun PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst destreg imm destdata

  32. “Addi” Instruction Operation rs rt imm # meaning What addi $5,$3,6 3 5 6 # $5 <- $3 + 6 registers do we read? rs 4 src1 src1data op/fun PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst destreg imm destdata

  33. “Addi” Instruction Operation rs rt imm # meaning Where do addi $5,$3,6 3 5 6 # $5 <- $3 + 6 we get the second input? 4 src1 src1data op/fun PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst destreg imm destdata

  34. “Addi” Instruction Operation rs rt imm # meaning addi $5,$3,6 3 5 6 Where do we # $5 <- $3 + 6 get the second input? 4 imm (16 bits ) src1 src1data op/fun PC Read Addr rs Out Data src2 src2data rt Instruction Register File rd Inst Memory destreg imm destdata 32 bits 16 bits

  35. Sign Extension • How do we go from 16-bit number to 32-bit number? • How about 4-bit to 8-bit. w 0111 = 7 = 00000111 w 1110 = -2 = 11111110 • Take the top bit and copy it to all the other bits

  36. “Addi” Instruction Operation rs rt imm # meaning Sign extend addi $5,$3,6 3 5 6 # $5 <- $3 + 6 immediate value 4 src1 src1data op/fun PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst destreg imm destdata 16 32 Sign Ext

  37. “Addi” Instruction Operation rs rt imm # meaning addi $5,$3,6 3 5 6 # $5 <- $3 + 6 How do we know which 4 register to write? src1 src1data op/fun PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst destreg imm destdata 16 32 Sign Ext

  38. “Addi” Instruction Operation rs rt imm # meaning addi $5,$3,6 3 5 6 # $5 <- $3 + 6 How do we know which 4 register to write? src1 src1data op/fun rt PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst destreg imm destdata 16 32 Sign Ext

  39. Putting them Together 4 src1 src1data op/fun PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst destreg imm destdata 16 32 Sign Ext

  40. Putting them Together Two wires to the same input 4 src1 src1data op/fun PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst destreg imm destdata 16 32 Sign Ext

  41. Putting them Together Two wires to the same input Add MUXs 4 src1 src1data op/fun PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst destreg imm destdata 16 32 Sign Ext

  42. Putting them Together What determines which to take? 4 src1 src1data op/fun PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst destreg imm destdata 16 32 Sign Ext

  43. Putting them Together What Control determines Unit ALUOp which to take? Op/Func code ALUSrc 4 RegDest src1 src1data op/fun PC Read Addr rs Out Data src2 src2data Instruction rt Register File rd Memory Inst destreg imm destdata 16 32 Sign Ext

Recommend

This Unit: Single-Cycle Datapath App App App Datapath storage elements System software

This Unit: Single-Cycle Datapath App App App Datapath storage elements System software

This Unit: Single-Cycle Datapath App App App Datapath storage elements System software MIPS Datapath CIS 371 MIPS Control Mem CPU I/O Computer Organization and Design Unit 4: Single-Cycle Datapath Based on slides by Prof. Amir

287 views • 14 slides
Lesson 10 Processors Continued Building a datapath Datapath element is a unit used to operate

Lesson 10 Processors Continued Building a datapath Datapath element is a unit used to operate

Lesson 10 Processors Continued Building a datapath Datapath element is a unit used to operate on or hold data within a processor. In the MIPS implementation, the datapath elements include the instruction and data memories, the register

1.07k views • 30 slides
ECE232: Hardware Organization and Design Lecture 11: Introduction to MIPs Datapath Adapted from

ECE232: Hardware Organization and Design Lecture 11: Introduction to MIPs Datapath Adapted from

ECE232: Hardware Organization and Design Lecture 11: Introduction to MIPs Datapath Adapted from Computer Organization and Design , Patterson &amp; Hennessy, UCB MIPS-lite processor Computer Processor IMemory (CPU) MIPS Want to build a

358 views • 21 slides
The Processor: Datapath and Control 3/ 24/ 2016 1 A single-cycle MIPS processor An

The Processor: Datapath and Control 3/ 24/ 2016 1 A single-cycle MIPS processor An

The Processor: Datapath and Control 3/ 24/ 2016 1 A single-cycle MIPS processor An instruction set architecture is an int erf ace that defines the hardware operations which are available to software. Any instruction set can be

714 views • 24 slides
CENG 3420 Lecture 06: Datapath Bei Yu byu@cse.cuhk.edu.hk CENG3420 L06.1 Spring 2018 The

CENG 3420 Lecture 06: Datapath Bei Yu byu@cse.cuhk.edu.hk CENG3420 L06.1 Spring 2018 The

CENG 3420 Lecture 06: Datapath Bei Yu byu@cse.cuhk.edu.hk CENG3420 L06.1 Spring 2018 The Processor: Datapath &amp; Control q We're ready to look at an implementation of the MIPS q Simplified to contain only: memory-reference

705 views • 39 slides
CS3350B Computer Organization Chapter 3: CPU Control &amp; Datapath Part 1: Introduction to MIPS

CS3350B Computer Organization Chapter 3: CPU Control &amp; Datapath Part 1: Introduction to MIPS

CS3350B Computer Organization Chapter 3: CPU Control &amp; Datapath Part 1: Introduction to MIPS Alex Brandt Department of Computer Science University of Western Ontario, Canada Thursday February 14, 2019 Alex Brandt Chapter 3: CPU Control

1.2k views • 118 slides
1 Well, plenty of registers But where should X, Y and SUM go? MIPS Memory (2 32 -1)

1 Well, plenty of registers But where should X, Y and SUM go? MIPS Memory (2 32 -1)

Behold the MIPS machine MIPS Memory The assembly language level (2 32 -1) . . . MIPS private regs PC (A+24) Introduction to MIPS IR (A+20) MIPS user regs (A+16) 0 0 0 0 $zero (A+12) $v0 (A+8)

447 views • 6 slides
1 Recall MIPS word size In hex 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12

1 Recall MIPS word size In hex 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12

Stored program computer MIPS Memory Forms of Address (2 32 -1) . . . MIPS private regs PC (A+24) MIPS machine code and addressing IR (A+20) modes MIPS user regs (A+16) 0 0 0 0 $zero (A+12) $v0

354 views • 7 slides
MIPS Architecture An Example: MIPS Example: subset of MIPS processor architecture From the

MIPS Architecture An Example: MIPS Example: subset of MIPS processor architecture From the

MIPS Architecture An Example: MIPS Example: subset of MIPS processor architecture From the Harris/Weste book Drawn from Patterson &amp; Hennessy MIPS is a 32-bit architecture with 32 registers Based on the MIPS-like processor from

339 views • 6 slides
Chapter Five 1 2004 Morgan Kaufmann Publishers The Processor: Datapath &amp; Control

Chapter Five 1 2004 Morgan Kaufmann Publishers The Processor: Datapath &amp; Control

Chapter Five 1 2004 Morgan Kaufmann Publishers The Processor: Datapath &amp; Control We're ready to look at an implementation of the MIPS Simplified to contain only: memory-reference instructions: lw, sw arithmetic-logical

1.19k views • 87 slides
EE 457 Unit 5 Single-Cycle CPU Datapath and Control 2 CPU Organization Scope We will build

EE 457 Unit 5 Single-Cycle CPU Datapath and Control 2 CPU Organization Scope We will build

1 EE 457 Unit 5 Single-Cycle CPU Datapath and Control 2 CPU Organization Scope We will build a CPU to implement our subset of the MIPS ISA Memory Reference Instructions: Load Word (LW) Store Word (SW) Arithmetic and Logic

700 views • 46 slides
IC220: Set #13: Building a real processor! ( Chapter 5) 1 The Processor: Datapath &amp; Control

IC220: Set #13: Building a real processor! ( Chapter 5) 1 The Processor: Datapath &amp; Control

IC220: Set #13: Building a real processor! ( Chapter 5) 1 The Processor: Datapath &amp; Control READING: 5.1 5.4 We're ready to look at an implementation of the MIPS Simplified to contain only: memory-reference

244 views • 8 slides
FSMD%Block%Diagram FSM$Datapath*Systems Datapath%Elements

FSMD%Block%Diagram FSM$Datapath*Systems Datapath%Elements

FSMD%Block%Diagram FSM$Datapath*Systems Datapath%Elements FSMD%Example%Requires%RAM,%Comparator,%Counter Altera%LPM%library%has%many%elements%useful%for% building%common%datapath%functions LPM_RAM_DQ%%

649 views • 19 slides
MIPS Q2 2018 16 August, 2018 1 MIPS in brief 60 45 60 28 active MIPS is a market leader

MIPS Q2 2018 16 August, 2018 1 MIPS in brief 60 45 60 28 active MIPS is a market leader

MIPS Q2 2018 16 August, 2018 1 MIPS in brief 60 45 60 28 active MIPS is a market leader in helmet solutions protecting the brain 15 brands 2 8 8 4 against rotational motion 2011 2012 2013 2014 2015 2016 2017 Patented

753 views • 12 slides
CSCI341 Lecture 30, Building a Datapath RECALL... The datapath is a representation of

CSCI341 Lecture 30, Building a Datapath RECALL... The datapath is a representation of

CSCI341 Lecture 30, Building a Datapath RECALL... The datapath is a representation of the flow of information (data, instructions) through the CPU Implemented as combination of circuitry and combinatorial &amp; sequential chips

404 views • 17 slides
CSCI-2500: Computer Organization Processor Design Datapath n The datapath is the interconnection

CSCI-2500: Computer Organization Processor Design Datapath n The datapath is the interconnection

CSCI-2500: Computer Organization Processor Design Datapath n The datapath is the interconnection of the components that make up the processor. n The datapath must provide connections for moving bits between memory, registers and the ALU.

2.24k views • 186 slides
LECTURE 5 Single-Cycle Datapath and Control PROCESSORS Datapath and control are the two

LECTURE 5 Single-Cycle Datapath and Control PROCESSORS Datapath and control are the two

LECTURE 5 Single-Cycle Datapath and Control PROCESSORS Datapath and control are the two components that come together to be collectively known as the processor. Datapath consists of the functional units of the processor. Elements

877 views • 54 slides
Datapath Design, Coding Standards, and Lab 2 1 Separating Control From Data The datapath is

Datapath Design, Coding Standards, and Lab 2 1 Separating Control From Data The datapath is

Datapath Design, Coding Standards, and Lab 2 1 Separating Control From Data The datapath is where data moves from place to place. Computation happens in the datapath No decisions are made here. Things you should find in a

276 views • 14 slides
MIPS ISA and MIPS Assembly CS301 Prof. Szajda Administrative HW #2 due Wednesday (9/11) at

MIPS ISA and MIPS Assembly CS301 Prof. Szajda Administrative HW #2 due Wednesday (9/11) at

MIPS ISA and MIPS Assembly CS301 Prof. Szajda Administrative HW #2 due Wednesday (9/11) at 5pm Lab #2 due Friday (9/13) 1:30pm Read Appendix B5, B6, B.9 and Chapter 2.5-2.9 (if you have not already done so!) MIPS ISA MIPS ISA

352 views • 24 slides
EE 109 Unit 10 MIPS Instruction Set MIPS INSTRUCTION OVERVIEW 10.3 10.4 Instruction Set

EE 109 Unit 10 MIPS Instruction Set MIPS INSTRUCTION OVERVIEW 10.3 10.4 Instruction Set

10.1 10.2 EE 109 Unit 10 MIPS Instruction Set MIPS INSTRUCTION OVERVIEW 10.3 10.4 Instruction Set Architecture (ISA) MIPS Processor and Bus Interface The MIPS processor can execute software instructions that will Defines the

225 views • 18 slides
Based on MIPS In fact, its based on the multi-cycle MIPS from Patterson and Hennessy

Based on MIPS In fact, its based on the multi-cycle MIPS from Patterson and Hennessy

Mini-MIPS From Weste/Harris CMOS VLSI Design Based on MIPS In fact, its based on the multi-cycle MIPS from Patterson and Hennessy Your CS/EE 3810 book... 8-bit version 8-bit data and address 32-bit instruction format 8

614 views • 27 slides
Pipelining Full Datapath Chapter 4 The Processor 2 Datapath With Control Chapter 4

Pipelining Full Datapath Chapter 4 The Processor 2 Datapath With Control Chapter 4

Pipelining Full Datapath Chapter 4 The Processor 2 Datapath With Control Chapter 4 The Processor 3 Performance Issues Longest delay determines clock period Critical path : load instruction Instruction memory

1.04k views • 86 slides
Exceptions, MIPS-Style Reminder: MIPS CPU deals with exceptions. Interrupts are

Exceptions, MIPS-Style Reminder: MIPS CPU deals with exceptions. Interrupts are

CPSC-410/611 Operating Systems Exceptions, MIPS-Style Reminder: MIPS CPU deals with exceptions. Interrupts are just a special case of exceptions. The MIPS Architecture has no interrupt-vector table! All exceptions trigger

574 views • 7 slides
The MIPS instruction set architecture The MIPS has a 32 bit architecture, with 32 bit

The MIPS instruction set architecture The MIPS has a 32 bit architecture, with 32 bit

The MIPS instruction set architecture The MIPS has a 32 bit architecture, with 32 bit instructions, a 32 bit data word, and 32 bit addresses. It has 32 addressable internal registers requiring a 5 bit register ad- dress. Register 0 always has

940 views • 72 slides

More recommend