ECE232: Hardware Organization and Design Lecture 11: Introduction to - PowerPoint PPT Presentation

ECE232: Hardware Organization and Design Lecture 11: Introduction to MIPs Datapath Adapted from Computer Organization and Design , Patterson & Hennessy, UCB

MIPS-lite processor Computer Processor IMemory (CPU) MIPS Want to build a processor for a Control  Instructions subset of MIPS instruction set (“MIPS - lite”) Datapath just enough to illustrate key • DMemory ideas instruction set subset (3 • groups): • arithmetic-logical: add, sub, and, or, slt • memory reference: lw, sw • control flow: j, beq • can we write real programs with just these? Need up to 5 steps to execute any  instruction in our subset ECE232: Intro to MIPs Datapath 2

Instruction Execution Steps Instruction 1. Read IM[PC] Fetch 2. Instruction Decode, PC = PC + 4, Decode, Inc PC and Register read Read Registers 3. ALU operation, Branch address ALU Operation, Branch address computation Data Memory 4. LW/STORE in Data memory operation 5. Register Write Write Back ECE232: Intro to MIPs Datapath 3

Building a Datapath for MIPS (step 1) Step 1: instruction fetch Instruction PC Memory Step 1  .  .  . add $t0,$t0,$t0 PC-4 Flow of add $t0,$s1,$t0 PC execution lw $t1,20($s0) PC+4 sw $t1,4($t0) PC+8  .  . ECE232: Intro to MIPs Datapath 4

Datapath Step 1: Any Instruction A d d “4” 32-bit adder or ALU wired only for add PC Address Instruction Instruction Memory Once program is loaded, (IMem) Clock IMem is read-only ECE232: Intro to MIPs Datapath 5

Building a Datapath for MIPS (step 2) Instruction PC Registers Memory Step 1 Step 2: Decode and Read Registers R add $t0,$s1,$t0 0 17 8 8 0 32 op rs rt rd shamt funct ECE232: Intro to MIPs Datapath 6

Datapath Step 2: Any Instruction R add $t0,$t1,$t2 op rs rt rd shamt funct Read Read Register 1 data 1 Read Instruction Register 2 Read Write data 2 Register Register Write File Data 6 Datapath Control Control Points ECE232: Intro to MIPs Datapath 7

Remaining Steps in Executing Instructions 3rd step onwards depends on instruction class  EX : for ALU instructions: add $t0, $t1, $t2  outputs from registers t1 and t2 will be sent to the ALU input For Memory-reference instruction:  lw $t0,20($s0) Address  Base + offset A L U ECE232: Intro to MIPs Datapath 8

Building a Datapath for MIPS ( lw step 3) A Instruction L PC Registers Memory U Step 1 Step 2 Step 3 I lw $t0, 20($s0) op rs rt address ECE232: Intro to MIPs Datapath 9

Datapath Step 3-4: R-format Instructions ALU control add, sub, and, or 3 Read Register 1 Read [$t1] data 1 A Instruction Zero Read L Register 2 U Result Write Read [$t2] Register data 2 [$t3]  [$t1]  [$t2] Write Registers Data RegWrite [$t1]  [$t2] 32 { +, -, AND, OR, etc.} ECE232: Intro to MIPs Datapath 10

Datapath Step 3: Branch beq $t0,$t1,loop PC + 4 from step 1 datapath A ALU control d Read 3 d Branch Register 1 Read [$t0] data 1 target Instruc- A Read Result tion L Register 2 U [$t1] Zero Write Read To Register data 2 branch Mult control Write Registers by logic Data 4 RegWrite Sign Extend 32 16 ECE232: Intro to MIPs Datapath 11

Steps 4,5 in Executing lw,sw 4th step depends on instruction class  lw $t1,20($s0) Ex: for lw: Fetch Data from Memory  sw $t1,4($t0) Data  Mem[Address] For sw: Put the contents of a register in Memory  A Instruction Data L PC Registers Memory Memory U Step 1 Step 2 Step 3 Step 4 From Register for SW To register for LW 5th step only for lw; rest are done  for lw: Write Result  Reg[rt]  Data ECE232: Intro to MIPs Datapath 12

Datapath Step 3-5: Load/Store lw $t0,24($s3) ALU control op rs rt address MemWrite Read Register 1 Read [$s3] data 1 Zero Instruc- A Read tion Read L Register 2 [$s3]+24 data U Address “24” Result Write Read Register data 2 DMem Write Registers Write Data Data RegWrite Sign MemRead Extend 16 32 ECE232: Intro to MIPs Datapath 13

Compose Datapath: R-form + Load/Store Add muxes ALU control MemWrite 3 Read Register 1 Read Instruction Read Zero data data 1 A Read MemTo- Register 2 L Reg U Address Read 0=R-form Write M data 2 1=L/S Register u DMem Registers x Write Write Data 1 Data M RegWrite ALUSrc u 0 = R-format MemRead Sign 1 = Load/Store x Extend 32 0 16 ECE232: Intro to MIPs Datapath 14

Compose Datapath: + IMem + PC a d “4” d MemWrite ALU control Read Read 4 Reg1 Read P Addr Read C Zero data data1 A Read Instruc- Reg2 L tion U Address Read MemTo- Write M data2 Reg Reg u IMem DMem Registers x Write Write Data Data M ALUSrc RegWrite u MemRead Sign x Extend 32 16 ECE232: Intro to MIPs Datapath 15

Compose Datapath: + Branch “Left Shift 2” M module a u a d d x “4” d << d PCSrc 2 MemWrite Read Read Reg1 ALUcon P Read Addr Read C data Zero data1 Read A Instruc- Reg2 L tion Address Read U MemTo- Write M data2 Reg Reg u IMem DMem Registers x Write Write Data Supports all Data M MIPS-lite ALUSrc RegWrite MemRead u instructions? Sign x (slt and ?) Extend 32 16 ECE232: Intro to MIPs Datapath 16

Datapath: Register fields Destination registers may differ across instruction formats:  • R-format: [rd]  [rs] op [rt] add $t0,$s0,$s1 For this instruction, bits 11-15 are the destination (t0), which should be connected to the write reg. inputs 6 bits 6 bits 5 bits 5 bits 5 bits 5 bits op rs rt rd shamt funct [rt]  mem [ [rs] + imm16 ] • I-format: lw $t0,24($s3) 6 bits 5 bits 5 bits 16 bits op rs rt offset For this instruction, bits 16-20 should go to the write reg. port. Bits 0-15 go to the ALU as address • Connection to the write reg . port changes! Solution? mux to the rescue!  ECE232: Intro to MIPs Datapath 17

Datapath (add RegDst Mux) M a u a d x d d 4 d << PCSrc 2 MemWrite 25:21 Read Read Addr Reg1 P Read Read C data Zero data1 Read 31:0 20:16 A Instruc- Reg2 tion L Address M Read U MemTo- Write M data2 u Reg Reg u DMem IMem x Regs x ALU- Write Write 15:11 con Data Data RegDst M ALU- RegWrite MemRead src u Sign 15:0 x Extend ECE232: Intro to MIPs Datapath 18

Datapath: Determine next PC What if instruction is a conditional branch ( beq )?  • if operands equal, take branch (PC gets PC+4+offset) • else PC gets PC+4 Therefore, set control point PCSrc = 1 if and only if beq and  Zero asserted ECE232: Intro to MIPs Datapath 19

Datapath (add Branch control point) M a u a d x d << d 4 d PCSrc 2 MemWrite 25:21 Read Read Branch Addr Reg1 P Read Read C Zero data data1 Read 31:0 20:16 A Instruc- Reg2 tion L Address Read M U MemTo- Write M data2 u Reg Reg u DMem IMem x Regs x ALU- Write Write 15:11 con Data Data RegDst M ALU- RegWrite MemRead src u Sign 15:0 x Extend ECE232: Intro to MIPs Datapath 20

Summary Clear understanding of ENGIN112 components is necessary  Review memories, registers, multiplexers, and ALUs, if necessary • The MIPs processor is built from the description of MIPs instructions  How do we physically execute each instruction? • Identify components that will perform the execution • Share the components • In this implementation, an “instruction execution” starts with the PC  and ends with the completion of the instruction For example, add two values from registers and write the value back to a • register Don’t get left behind  Today’s material is critical to the next five weeks of the course • ECE232: Intro to MIPs Datapath 21