Microprocessors & Interfacing AVR Instructions & - PowerPoint PPT Presentation

Lecture Overview • AVR ISA Microprocessors & Interfacing • AVR Instructions & Programming (I) – Basic construct implementation AVR ISA & AVR Programming (I) Lecturer : Dr. Annie Guo S2, 2008 COMP9032 Week2 1 S2, 2008 COMP9032 Week2 2 Atmel AVR AVR Registers • 8-bit RISC architecture • General purpose registers – Most instructions have 16-bit fixed length – 32 8-bit registers, R0 ~ R31 or r0 ~ r31 – Most instructions take 1 clock cycle to execute. – Can be further divided into two groups • First half group: R0 ~ R15 and second half group: R16 ~ • Load-store memory access architecture R31 – All calculations are on registers • Some instructions work only on the second half group R16~R31 • Internal program memory and data memory – Due to the limitation of instruction encoding bits • Wide variety of on-chip peripherals (digital » Will be covered later I/O, ADC, EEPROM, UART, pulse width – E.g. ldi rd, #number ;rd ∈ R16~R31 modulator (PWM), …). S2, 2008 COMP9032 Week2 3 S2, 2008 COMP9032 Week2 4

AVR Registers (cont.) AVR Registers (cont.) • I/O registers • General purpose registers – 64 8-bit registers – The following register pairs can work as address • Their names are defined in the m64def.inc file indexes – Used in input/output instructions • X, R27:R26 • Mainly storing data/addresses and control signal bits • Y, R29:R28 – Some instructions work only with I/O registers, • Z, R31:R30 others with general purpose registers – don’t – The following registers can be applied for specific confuse them use • E.g. in rd, port ; port must be an I/O register • R1:R0 store the result of multiplication instruction – Will be covered in detail later • R0 stores the data loaded from the program memory • Status register (SREG) – A special I/O register S2, 2008 COMP9032 Week2 5 S2, 2008 COMP9032 Week2 6 The Status Register in AVR The Status Register in AVR (cont.) • The Status Register (SREG) contains information about the result of the most recently executed I T H S V N Z C arithmetic instruction. This information can be used for altering program flow in order to perform Bit 7 6 5 4 3 2 1 0 conditional operations. • SREG is updated after any of ALU operations by • Bit 7 – I: Global Interrupt Enable hardware. – Used to enable and disable interrupts. • SREG is not automatically stored when entering an – 1: enabled. 0: disabled. interrupt routine and restored when returning from an – The I-bit is cleared by hardware after an interrupt interrupt. This must be handled by software. has occurred, and is set by the RETI instruction to – Using in/out instruction to store/restore SREG enable subsequent interrupts. S2, 2008 COMP9032 Week2 7 S2, 2008 COMP9032 Week2 8

The Status Register in AVR (cont.) The Status Register in AVR (cont.) I T H S V N Z C I T H S V N Z C Bit 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 0 • Bit 6 – T: Bit Copy Storage – The Bit Copy instructions BLD (Bit LoaD) and BST • Bit 5 – H: Half Carry Flag (Bit STore) use the T-bit as source or destination – The Half Carry Flag H indicates a Half Carry for the operated bit. A bit from a register in the (carry from bit 4) in some arithmetic operations. Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit – Half Carry is useful in BCD arithmetic. in a register in the Register File by the BLD instruction. S2, 2008 COMP9032 Week2 9 S2, 2008 COMP9032 Week2 10 The Status Register in AVR (cont.) The Status Register in AVR (cont.) I T H S V N Z C I T H S V N Z C Bit 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 0 • Bit 4 – S: Sign Bit • Bit 2 – N: Negative Flag – Exclusive OR between the Negative Flag N and – N is the most significant bit of the result. the Two’s Complement Overflow Flag V ( S = N ⊕ V). • Bit 1 – Z: Zero Flag • Bit 3 – V: Two’s Complement Overflow Flag – Z indicates a zero result in an arithmetic or logic operation. 1: zero. 0: Non-zero. – The Two’s Complement Overflow Flag V supports two’s complement arithmetic. S2, 2008 COMP9032 Week2 11 S2, 2008 COMP9032 Week2 12

The Status Register in AVR (cont.) AVR Address Spaces • Three address spaces – Data memory I T H S V N Z C • Storing data to be processed Bit 7 6 5 4 3 2 1 0 – Program memory • Storing program code and some constants – EEPROM memory • Bit 0 – C: Carry Flag • Large permanent data storage – Its meaning depends on the operation. • For addition X+Y, it is the carry from the most significant bit • For subtraction x-y, where x and y are unsigned integers, it indicates whether x<y or not. If x<y, C=1; otherwise, C=0. S2, 2008 COMP9032 Week2 13 S2, 2008 COMP9032 Week2 14 Data Memory Space Program Memory Space • Covers • Covers Data Memory Program Memory – Register file 0x0000 – 16 bit Flash Memory 32 General purpose 0x0000 Working Registers • I.e. registers in the register • Read only file also have memory 0x1F – Instructions are Program Flash Memory address 0x20 retained when power 64 Input/Output (1K bytes~128K bytes) – I/O registers Registers off 0x5F • I.e. I/O registers have two – Can be accessed with 0x60 versions of addresses 16 Bits Internal SRAM special instructions – I/O addresses (128~4K bytes) • LPM – Memory addresses – SRAM data memory • SPM External SRAM • The highest memory End Address 8 bits location is defined as RAMEND End Address S2, 2008 COMP9032 Week2 15 S2, 2008 COMP9032 Week2 16

EEPROM Memory Space AVR Instruction Format • Covers • For AVR, almost all instructions are 16 bits – 8-bit EEPROM long Data EEPROM Memory memory – For example, 0x0000 • Use to permanently • add Rd, Rr store large set of data • sub Rd, Rr – Can be accessed EEPROM Memory • mul Rd, Rr using load and store (64~4K bytes) instructions with • brge k special control bit 8 bits • Few instructions are 32 bits long settings – For example • Not covered in this • lds Rd, k ( 0 ≤ k ≤ 65535 ) course – loads 1 byte from the SRAM to a register. End address S2, 2008 COMP9032 Week2 17 S2, 2008 COMP9032 Week2 18 Examples (1) Examples (2) - 16 bits long - 32 bit long • Clear register instruction • Unconditional branch Syntax: clr Rd Syntax: jmp k Operand: 0 ≤ k < 4M Operand: 0 ≤ d ≤ 31 Operation: Rd ← 0 Operation: PC ← K • Instruction format • Instruction format 0 0 1 0 0 1 d d d d d d d d d d 1 0 0 1 0 1 0 k k k k k 1 1 0 k 15 0 0 15 – OpCode uses 6 bits (bit 10 to bit 15). k k k k k k k k k k k k k k k k – The operand uses the remaining 10 bits (only 5 bits, bit 0 to bit 4, are actually needed). 16 31 • Execution time • Execution time 3 clock cycles 1 clock cycle S2, 2008 COMP9032 Week2 19 S2, 2008 COMP9032 Week2 20

Examples (3) AVR Instructions - with variable cycles • Conditional branch • AVR has the following classes of instructions: Syntax: breq k – Arithmetic and Logic Operand: -64 ≤ k < +63 – Data transfer Operation: If Rd=Rr(Z=1) then PC ← PC+k+1, else – Program control PC � PC+1 – Bit and Others • Instruction format • Bit and Bit test • MCU Control 1 1 1 1 0 0 k k k k k k k 0 0 1 • An overview of the instructions are given in • Execution time the next slides. 1 clock cycle if condition is false 2 clock cycles if condition is true S2, 2008 COMP9032 Week2 21 S2, 2008 COMP9032 Week2 22 AL Instructions Transfer Instructions • Memory • Arithmetic • Logic • GP register – Data memory – addition • E.g. AND Rd, Rr • E.g. MOV Rd, Rr • E.g. LD Rd, X ST X, Rr • E.g. ADD Rd, Rr • Shift • I/O registers – Program memory – Subtraction • E.g. LSL Rd • E.g. IN Rd, PORTA • E.g. LPM • E.g. SUB Rd, Rr OUT PORTB, Rr – EEPROM memory – Increment/decrement • Stack • Not covered in this course • E.g INC Rd • PUSH Rr – Multiplication • POP Rd • E.g. MUL Rd, Rr • Immediate values • E.g. LDI Rd, K8 S2, 2008 COMP9032 Week2 23 S2, 2008 COMP9032 Week2 24