Microprocessors & Interfacing Interrupt system specifications - PowerPoint PPT Presentation

Lecture Overview • Introduction to Interrupts Microprocessors & Interfacing – Interrupt system specifications – Multiple sources of interrupts – Interrupt priorities Interrupts (I) • Interrupts in AVR – Interrupt vector table – Interrupt service routines – System reset Lecturer : Dr. Annie Guo • Watchdog reset S2, 2008 COMP9032 Week6 1 S2, 2008 COMP9032 Week6 2 CPU Interacts with I/O Interrupt Systems Two approaches: • An interrupt system implements interrupt • Polling services – Software queries I/O devices • It basically performs three tasks: – No hardware needed – Recognize interrupt events – Not efficient – Respond to the interrupts • CPU may waste processor cycles to query a device even if it does not need any service. – Resume normal programmed task • Interrupts – I/O devices generate signals to request services from CPU Need special hardware to implement interrupt services – Efficient • A signal is generated only if the I/O device needs services from CPU. S2, 2008 COMP9032 Week6 3 S2, 2008 COMP9032 Week6 4

Recognize Interrupt Events Respond to Interrupts • Interrupt events • Handling interrupt – Associated with interrupt signals: – Wait for the current instruction to finish. • In different forms, including signal levels and edges. – Acknowledge the interrupting device. – Can be multiple and synchronous – Branch to the correct interrupt service routine • Namely, there may be many sources to generate an (interrupt handler) to service interrupting device. interrupts; a number of interrupts can be generated at the same time. • Approaches are required to – Identify an interrupt event among multiple sources – Determine which interrupts to serve if there are multiple simultaneous interrupts S2, 2008 COMP9032 Week6 5 S2, 2008 COMP9032 Week6 6 Resume Normal Task Interrupt Process Control • Return to the interrupted program at the point • Interrupts can be enabled or disabled it was interrupted. • Can be controlled in two ways: – Software control • Allow programmers to enable and disable selected/all interrupts. – Hardware control • Disable further interrupts while an interrupt is being serviced S2, 2008 COMP9032 Week6 7 S2, 2008 COMP9032 Week6 8

Interrupt Recognition and Interrupt Recognition and Ack. Acknowledgement Hardware Pending • An Interrupt Request (IRQ) may occur at any time. Interrupt IRQ-FF IRQ Signal Interrupt signal to Set INTERR- – It may have rising or falling edges or high or low levels. conditioning sequence Reset UPTING controller – Frequently it is an active-low signal DEVICE Interrupt ack from • multiple devices are wire-ORed together. sequence • Signal Conditioning Circuit detects these different controller INTE-FF types of signals. Interrupt SEQUENCE Set Enable Reset CONTROLLER • Interrupt Request Flip-Flop (IRQ-FF) records the interrupt request until it is acknowledged. Disable interrupt instruction – When IRQ-FF is set, it generates a pending interrupt signal that goes towards the Sequence Controller. Enable interrupt instruction – IRQ-FF is reset when CPU acknowledges the interrupt with INTA signal. Return from interrupt CPU instruction S2, 2008 COMP9032 Week6 9 S2, 2008 COMP9032 Week6 10 Interrupt Recognition and Ack. Interrupt Recognition and Ack. (cont.) (cont.) • An interrupt acknowledge signal is generated by the • Interrupts can be enabled and disabled by software CPU when the current instruction has finished instructions, which is supported by the hardware execution and CPU has detected the IRQ. Interrupt Enable Flip-Flop (INTE-FF). – This resets the IRQ-FF and INTE-FF and signals the • When the INTE-FF is set, all interrupts are enabled interrupting device that CPU is ready to execute the and the pending interrupt is allowed through the AND interrupting device routine. gate to the sequence controller. • At the end of the interrupt service routine, CPU executes a return-from-interrupt instruction. • The INTE-FF is reset in the following cases. – Part of this instruction’s job is to set the INTE-FF to re- – CPU acknowledges the interrupt. enable interrupts. – CPU is reset. • Nested interrupts can happen If the INTE-FF is set – the Disable Interrupt Instruction is executed. during an interrupt service routine – An interrupt can therefore interrupt interrupting interrupts. S2, 2008 COMP9032 Week6 11 S2, 2008 COMP9032 Week6 12

Multiple Sources of Interrupts Polled Interrupts • To handle multiple sources of interrupts, the • Software, instead of hardware, is responsible interrupt system must for finding the interrupting source. – Identify which device has generated the IRQ. – The device must have logic to generate the IRQ signal and to set an “I did it” bit in a status register • Using polling approach that is read by CPU. • Using vectoring approach – Resolve simultaneous interrupt requests – The bit is reset after the register has been read. • using prioritization schemes. S2, 2008 COMP9032 Week6 13 S2, 2008 COMP9032 Week6 14 Polled Interrupt Execution Flow Polled Interrupt Logic IRQ Device generates IRQ Logic to Logic to reset IRQ generate IRQ when status CPU polls register is read status registers SW of all devices Logic to set “I Logic to read did it” bit status register and CPU found reset “I did it” bit Status register the interrupting device Data CPU executes Address the service routine for that device Control S2, 2008 COMP9032 Week6 15 S2, 2008 COMP9032 Week6 16

Vectored Interrupting Device Vectored Interrupts Hardware INTA • CPU’s response to IRQ is to assert INTA. IRQ • The interrupting device uses INTA to place information that identifies itself, called vector, Logic to reset Logic to IRQ onto the data bus for CPU to read. generate IRQ • CPU uses the vector to execute the interrupt Vector Information service routine. Three-State Driver HW Data Address Control S2, 2008 COMP9032 Week6 17 S2, 2008 COMP9032 Week6 18 Multiple Interrupt Masking Multiple Interrupt Masking Circuit • CPU has multiple IRQ input pins. IRQ 0 IRQ 1 • Masking enables some interrupts and IRQ 2 disables other interrupts CPU ••• • CPU designers reserve specific memory IRQ n locations for a vector associated with each IRQ line. • Individual disable/enable bit is assigned to each interrupting source. S2, 2008 COMP9032 Week6 19 S2, 2008 COMP9032 Week6 20

Interrupt Priorities Software Resolution • When multiple interrupts occur at the same Device generates time, which one will be serviced first? IRQ • Two resolution approaches: CPU polls – Software resolution status registers SW • Polling software determines which interrupting source is of all devices serviced first. – Hardware resolution CPU found • Daisy chain. the interrupting device Selection • Others Algorithm CPU executes the service routine for that device S2, 2008 COMP9032 Week6 21 S2, 2008 COMP9032 Week6 22 Daisy Chain Priority Resolution Daisy Chain Priority Resolution (cont.) IRQ • CPU asserts INTA that is passed down the chain from device to device. The higher- priority device is closer to CPU. INTA INTA INTA INTA CPU Device 1 Device 2 • • • Device n • When the INTA reaches a device that generated the IRQ, that device puts its vector Data on the data bus and does not pass along the Address INTA. So lower-priority devices do NOT Control receive the INTA. S2, 2008 COMP9032 Week6 23 S2, 2008 COMP9032 Week6 24

Transferring Control to Interrupt Interrupt Service Routine Service Routine • Hardware needs to save the return address. • A sequence of code to be executed when the corresponding interrupt is responded by CPU. – Most processors save the return address on the stack. • Interrupt service routine is a special • Hardware may also save some registers such subroutine, therefore can be constructed with as program status register. three parts: – AVR does not save any register. It is – Prologue: programmers’ responsibility to save program • Code for saving conflict registers on the stack. status register and conflict registers. – Body: • The delay from the time the IRQ is generated • Code for doing the required task. by the interrupting device to the time the – Epilogue: Interrupt Service Routine (ISR) starts to • Code for restoring all saved registers from the stack. execute is called interrupt latency . • The last instruction is the return-from-interrupt instruction. S2, 2008 COMP9032 Week6 25 S2, 2008 COMP9032 Week6 26 Software Interrupt Exceptions • Software interrupt is the interrupt generated by • Abnormalities that occur during the normal software without a hardware-generated-IRQ. operation of the processor. • Software interrupt is typically used to implement – Examples are internal bus error, memory access system calls in OS. error and attempts to execute illegal instructions. • Some processors have a special machine instruction • Some processors handle exceptions in the to generate software interrupt. same way as interrupts. – SWI in ARM. – AVR does not handle exceptions. • AVR does NOT provide a software interrupt instruction. – Programmers can use External Interrupts to implement software interrupts. S2, 2008 COMP9032 Week6 27 S2, 2008 COMP9032 Week6 28