Logically Determined Design and Flow Computing with With NULL - PowerPoint PPT Presentation

Logically Determined Design and Flow Computing with With NULL Convention Logic First Principles Karl Fant Feb, 2015 Materials of this conversation, slides and circuit movie, can be downloaded from karlfant.net/ytvideo

The NULL Convention Given an element with two distinct states such as high and low voltage on an electronic wire we assign one state to mean “data” and the other state to mean “not data”, which we will call NULL. This is in contrast to assigning both states a data meaning such as 0,1 or True, False. The Multi-rail Convention With only one data state data variables will be multi-rail encoded. A binary variable will be dual-rail encoded with two wires, one meaning 0 the other meaning 1, only one of which will be data at a time. The Completeness Convention We define patterns of each state that represent completeness. Consider the output of a dual- rail ripple carry adder which begins with all rails null. Inputs transition to data and output rails begin transitioning to data. When the add is done exactly one rail of each output dual-rail variable has transitioned to data which is a data state completeness pattern upon the occurrence of which the input can begin transitioning to null. All output rails transitoned to null is a null state completeness pattern upon the occurrence of which the input can begin transitioning to data and so on... data flow data flow data flow completeness completeness completeness (done) (done) (done) (empty) (empty) (empty) (empty) null flow null flow null flow null flow completeness completeness completeness completeness Page 2

NULL Convention Logic (NCL) A Dual threshold logic with state holding behavior. Logic operators with a completeness threshold for DATA and a completeness threshold for NULL: • transitions its output to DATA only when its data threshold is met, • transitions its output to NULL only when its input is completely NULL and • maintains its output when its input is between the two thresholds 2 0f 2 3 0f 3 2 0f 3 4 0f 4 3 0f 4 DD DN ND NN DD DN ND NN – – – D D – D D DD DD D N DD DN ND NN DD DN ND NN – – – – D D – – – – – D – – – D D D DN DN D D D – – – – – – – – – – – D – – – N N N ND ND N N N – – – – – – NN N NN N – no transition 2 3 2 4 3 DATA completeness NULL completeness (threshold met), (empty), 3 3 3 3 3 output to DATA (done) awaiting Data transition DATA awaiting NULL transition transitioning begins NULL completeness (threshold met), 3 3 3 3 3 3 output to NULL (empty) NULL awaiting Data transition transitioning begins Page 3

NCL Dual Threshold Logic Functions A A A TH34W32 A TH14 B TH44W2 B 1. A 1 B 3 4 C C C D D D TH12 22. A + BC + BD 9. A + B + C + D A 1 15. ABC + ABD + ACD B A 2. A + B TH54W32 B 5 A A TH24 C B TH34W3 B D 2 TH22 A 3 C 2 23. AB + ACD C B D D 3. AB 16. A + BCD 10. AB + AC + AD + BC + BD + CD A TH44W322 B 4 C TH13 A A TH44W3 D D B A B 1 TH34 4 24. AB + AC + AD + BC B C C 3 D 4. A + B + C C 17. AB + AC + AD D A TH54W322 B 11. ABC + ABD + ACD + BCD 5 TH23 C A A TH24W22 2 D D B B 2 25. AB + AC + BCD C C A TH44 D 5. AB + BC + AC B 4 18. A + B + CD A C 2 THXOR B D 1 A C A TH34W22 TH33 2 12. ABCD D 3 B B 3 C C 26. AB + CD D 6. ABC A TH24W2 A 19. AB + AC + AD + BC + BD B THAND 2 2 B C A TH23W2 A TH44W22 2 1 D 2 C B B 4 D 13. A + BC + BD + CD C C 2 D 7. A + BC 27. AB + BC + AD 20. AB + ACD + BCD A TH34W2 A B THCOMP TH33W2 A 3 TH54W22 A 3 C B B 1 B 5 D 2 C C C 1 D D 8. AB + AC 14. AB + AC + AD + BCD 21. ABC + ABD 28. AC + BC + AD + BD Page 4

The multi-rail convention With only one data value, an M value variable is expressed with M rails only one of which will express its DATA value at a time. Wire numeric base 2 meanings Logical meanings Wire NULL 0 1 NULL TRUE FALSE #1 N D N #1 N D N #2 N N D #2 N N D Wire general meanings Wire numeric base 4 meanings NULL Animal Vegetable Mineral NULL 0 1 2 3 #1 N D N N #1 N D N N N #2 N N D N #2 N N D N N #3 N N N D #3 N N N D N #4 N N N N D Wire control meanings Wire NULL Select A Select B Select C numeric base 10 meanings NULL 1 2 3 4 5 6 7 8 9 0 #1 N D N N #1 #2 N N D N N D N N N N N N N N N #3 N N N D #2 N N D N N N N N N N N #3 N N N D N N N N N N N #4 N N N N D N N N N N N Wire other meanings #5 N N N N N D N N N N N NULL First Second Third Fourth #6 N N N N N N D N N N N #1 N D N N N #7 N N N N N N N D N N N #2 N N D N N #8 #3 N N N D N N N N N N N N N D N N #4 N N N N D #9 N N N N N N N N N D N #10 N N N N N N N N N N D Page 5

Movie discusion Page 6

Self Coordination: The Oscillation Completeness is fed back with inversion (closure) creating an oscillation with: • one or more sources, • a completeness flow path and • one or more destinations oscillation period 20 gate delays links data path latency 7 gate delays 0 2 1 oscillation CI 1 1 26 cells 2 closure 11-13 signal transitions closure 0 00 00 2 2 2 1 A 1 0 1 2 1 01 01 S 2 1 2 2 1 1 closure 1 2 10 10 00 0 link 2 2 0 1 0 1 2 closure 2 B 11 11 1 1 01 2 0 1 2 2 1 half-adder half-adder 2 2 1 CO 1 closure 1 10 2 0 2 link 1 11 2 OR circuit input 2 boundary closure The oscillation Link coordinates flow from oscillation to oscillation When linked oscillations present data to a link it will pass a data wave and maintain the data wave until the oscillations present null When linked oscillations present null to a link it will pass a null wave and maintain the null wave until the oscillations present data The expression is purely in terms of logical relationships Page 7

Since the combinational expression and the link are both in terms of logical relations they can be optimized together oscillation period 20 gate delays data path latency 7 gate delays 1 oscillation links 26 cells 0 2 11-13 signal transitions CI 1 2 1 closure closure 00 00 0 2 2 2 1 1 A 0 1 2 01 1 01 2 S 1 2 2 1 1 1 2 closure 10 10 00 2 0 link 2 1 1 0 2 closure 0 2 11 11 B 1 1 01 2 2 0 2 1 half-adder half-adder 2 1 2 1 CO 1 closure 10 1 2 0 2 link 1 11 2 OR 2 closure oscillation period 18 gate delays links integrate combinational logic and link data path latency 6 gate delays 2 0 1 oscillation 1 CI 24 cells 2 1 10-12 signal transitions closure link closure 00 00 2 0 2 2 1 1 0 2 1 A S 1 01 01 2 1 2 2 1 1 1 2 closure 10 10 00 0 2 2 1 0 1 3 closure 2 0 11 half-adder 11 half-adder 1 B 1 01 2 0 2 1 3 2 1 1 CO 1 1 closure 10 0 3 OR 1 11 3 2 closure link Page 8

Other combinational ranks can be made a link oscillation period 18 gate delays links data path latency 6 gate delays 1 oscillation 2 0 1 CI 24 cells 2 1 10-12 signal transitions closure link closure 00 00 2 0 2 2 1 1 0 2 1 A S 1 01 01 1 2 2 2 1 1 1 2 closure 10 10 00 2 0 2 1 1 0 3 closure 2 0 11 half-adder 11 1 B half-adder 1 01 2 2 0 1 3 1 2 1 CO 1 1 closure 10 0 3 OR 1 11 3 2 closure link oscillation period 12 gate delays finer oscillation granularity data path latency 6 gate delays links 3 oscillations 3 35 cells 0 2 2 19-21 signal transitions CI 1 1 2 1 2 2 link closure closure 00 00 0 2 3 3 1 1 0 2 A 1 1 1 S 1 1 01 01 2 3 3 1 1 1 2 closure 10 10 00 0 3 3 1 0 1 3 closure 0 2 1 1 11 B half-adder 11 half-adder 1 1 01 3 0 3 1 1 3 2 1 CO 1 1 10 closure 0 2 3 link OR 1 1 11 2 3 3 link link Page 9