Chapter 1 Combinational Logic Process Control Ch 1- 1 Flaxer Eli - - PDF document

Flaxer Eli - Process Control

Ch 1- 1

Chapter 1

Combinational Logic

Process Control

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Chapter Outline

• Documentation Standards for digital systems.
• Combinational Logic Design Structures :
• Logic Gates
• Decoders
• Encoders
• Three-State Buffers
• Multiplexers
• Demultiplexers
• Adders

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Basic logic Gates

Y X Z X Y Z Z X

X Y Z X Y Z X Z 1 1 1 1 1 1 1 1 1 1 1 1 1 1

AND OR NOT

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No Basic logic Gates

X Y Z X Y Z 1 1 1 1 1 1 1 1 1 1 1 1

NAND NOR

X Y Z X Y Z

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No Basic logic Gates

X Y Z X Y Z 1 1 1 1 1 1 1 1 1 1 1 1

XOR NXOR

X Y Z X Y Z

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Timing Diagrams

• Delay depends on
• Internal circuit structure
• Logic Family type
• Source Voltage
• Temperature

OUT IN /ENABLE Logic Circuit IN /ENABLE OUT

tOUT

IN /ENABLE OUT

tOUTmin tOUTmax

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Timing Diagram for Data signals (Bus)

• t1 : t setup
• t2 : t OUTmin
• t3 : t OUTmax
• t4 : t hold

IN /WRITE Logic Circuit (Memory) OUT IN /WRITE OUT t1 t2 t3 t4

• ld data

new data new data

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Decoder

• Multiple-input/multiple-output device.
• Inputs ( n ) are less than outputs ( m ).
• Converts input code words into output

code words.

• One-to-One mapping :
• Each input code produces only one
• utput code.
• Input codes :
• Binary Code
• Gray Code
• BCD Code
• Your Code !
• utput

code input code enable inputs DECODER

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Binary Decoder

• n-to-2^n decoder : n inputs and 2^n outputs.
• Input code : Binary Code.
• Output code : 1-out-of-2^n , One output is asserted for each input

code.

• Example : n=2, 2-to-4 decoder
• Inputs Outputs

EN I1 I0 Y3 Y2 Y1 Y0 0 x x 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0

EN I0 I1 Y0 Y1 Y2 Y3

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Encoders

• Multiple-input/multiple-output device.
• Perfoms the inverse function of a Decoder.
• Outputs ( m ) are less than inputs ( n ).
• Converts input code words into output

code words.

• utput

code input code ENCODER

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Binary Encoder

• 2^n-to-n encoder : 2^n inputs and n outputs.
• Input code : 1-out-of-2^n.
• Output code : Binary Code
• Example : n=3, 8-to-3 encoder

Inputs Outputs I0 I1 I2 I3 I4 I5 I6 I7 Y0 Y1 Y2 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1

I1 I2 I3 Y1 Y2 I4 I5 I6 I0 Y0 I7 Binary encoder

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Priority Encoder

• 74x148

Inputs Outputs /EI /I0 /I1 /I2 /I3 /I4 /I5 /I6 /I7 /A2 /A1 /A0 /GS /EO 1 x x x x x x x x 1 1 1 1 1 0 x x x x x x x 0 0 0 0 0 1 0 x x x x x x 0 1 0 0 1 0 1 0 x x x x x 0 1 1 0 1 0 0 1 0 x x x x 0 1 1 1 0 1 1 0 1 0 x x x 0 1 1 1 1 1 0 0 0 1 0 x x 0 1 1 1 1 1 1 0 1 0 1 0 x 0 1 1 1 1 1 1 1 1 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0

• /GS is asserted if any of the inputs is selected
• /EO is asserted when no input is selected ( used for cascading encoders )

I7 I6 I5 A1 A0 I4 I3 I2 EI A2 I1 74x148 I0 GS EO

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Three State Buffers/Drivers

• A buffer/inverter with enable input

Buffer Buffer Inverter Inverter Actice High Enable Actice Low Enable Active High Enable Actice Low Enable

• The ouput is floating ( High Impedance, Hi-Z ) when the enable input

is deasserted ( The input is isolated from the output )

• Application:

Controlling the access of a single line/bus by multiple devices

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Multiplexers

• Multiplexing : transmitting large number of signals over a small

number of channels or lines

• Digital multiplexer (MUX ) : selects one of many input lines and

directs it to a single output.

• Selection lines controls the selection of a particular input
• n selction lines, 2^n inputs , single output.
• Example : 4-to-1 line multiplexer :
• Function Table :

S1 S0 Y 0 0 I0 0 1 I1 1 0 I2 1 1 I3

4 1 × MUX I0 Y S1 S0

Inputs Output Select

I1 I2 I3

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Demultiplexers

• Demultiplexer (DMUX) performs the opposite function of a MUX.
• A digital Demultiplexer receives input data on a single input and

transmits it on one of 2^n possible outputs according to the value of the n select inputs

• MUX/DMUX are used in data transmission

Source Destination

MUX DMUX

A B C A B C

Select Select

BUS

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1-to-4 DMUX

• 1-to-4 DEMUX

Function Table IN S1 S0 D0 D1 D2 D3 x 0 0 IN 0 0 0 x 0 1 0 IN 0 0 x 1 0 0 0 IN 0 x 1 1 0 0 0 IN

1 4 × DMUX

D0 IN S1 S0

Input Outputs Select

D1 D2 D3

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Half Adder

• Truth table :

X Y S=(X+Y) CO 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1

• CO

X Y =

• S

X Y = ⊕

Y X S CO

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Full Adder

• Truth Table

0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

• S = X’Y’CIN+ X’YCIN’+XY’CIN’+XYCIN

=

• COUT=XY+X CIN+Y CIN

X Y CIN S COUT

S X Y CIN = ⊕ ⊕

CIN Y X S COUT X Y COUT CIN S