IIT Bombay CDEEP Autumn 2009 GHDL- VHDL Simulator Presented by- - PowerPoint PPT Presentation

IIT Bombay CDEEP Autumn 2009 GHDL- VHDL Simulator Presented by- Anil Powai Labs Tech. Pvt. Ltd. EE705/707 Lecture No. 22 Prof. Maryam Shojaei Baghini

IIT Bombay GHDL : VHDL Simulator • GHDL is a VHDL compiler that can execute (simulate) a VHDL program. • Features of GHDL: – GHDL directly translates a VHDL file to machine code. – Faster compilation and analysis of code. – Produces a VCD file which can be viewed with a wave viewer. – GHDL aims at implementing VHDL as defined by IEEE 1076. – It supports most of the 1987 standard and most features added by the 1993 standard. EE705/707 Lecture No. 22 Prof. Maryam Shojaei Baghini

IIT Bombay Starting with GHDL • The use of the GHDL compiler is demonstrated by simulating the following examples. – Full Adder (Behavioural) example with single library. – Full-adder (Structural) example with multiple libraries. • The general concept is to first analyze the VHDL files using the GHDL compiler – This creates an executable. • The executable is then run directly to achieve the simulation. EE705/707 Lecture No. 22 Prof. Maryam Shojaei Baghini

IIT Bombay Full Adder (Behavioural) example using single library • Full adder is described in the file ‘full_adder.vhdl’ : – It is behavioural description of full adder using two concurrent assignments for sum (s) and carry_out (co) outputs. • Test bench for entity ‘full_adder’ is described in the file full_adder_tb.vhdl. – Full_adder_tb.vhdl is self checking test bench. EE705/707 Lecture No. 22 Prof. Maryam Shojaei Baghini

IIT Bombay Full Adder (Behavioral) example using single library • Steps to simulate the design are given below: – Analysis of design and testbench files : Commands given below are used to analyze the design files present in directory RTL/ and TB/. VHDL files present in directories RTL/ and TB/ are compiled into library ‘work’. • ghdl -a --work=work RTL/full_adder.vhdl • ghdl -a --work=work TB/testbench.vhdl – Elaboration of design and testbench : command given below will create the executable with ‘testbench’ name. • ghdl -e --work=work testbench – Runing simulation: command given below is used to run executable for 1 ms and dump simulation results into file output.vcd. • ghdl -r testbench --stop-time=1ms --vcd=output.vcd – To observe waveform use following command. • gtkwave output.vcd EE705/707 Lecture No. 22 Prof. Maryam Shojaei Baghini

IIT Bombay Simulation Results EE705/707 Lecture No. 22 Prof. Maryam Shojaei Baghini

IIT Bombay Full Adder (Structural) example using multiple libraries • Full adder is described in the file ‘full_adder.vhdl’ : – It is structural description of full adder using ‘or_gate’, ‘xor_gate’ and ‘and_gate’ components. – ‘xor_gate’ and ‘and_gate’ are referred from library ‘work’ , while ‘or_gate’ is referred from library ‘lib1’. – Package ‘component_package_work’ has component declaration of ‘xor_gate’ and ‘and_gate’. This package need to compile in library ‘work’. – Package ‘component_package_lib1’ has component declaration of ‘or_gate’ . This package needs to be compiled in library ‘lib1’. • Test bench for entity ‘full_adder’ is described in the file full_adder_tb.vhdl. • full_adder_tb.vhdl and full_adder.vhdl need to be compiled in library ‘work’. EE705/707 Lecture No. 22 Prof. Maryam Shojaei Baghini

IIT Bombay Full Adder (Structural) example using multiple libraries • Steps to simulate the design are given below: – Analysis of design and test bench files : Commands given below are used to analyze the design files present in directory LIB1/, RTL/ and TB/. VHDL files present in LIB1/ are compiled in library ‘lib1’, while VHDL files present in directories RTL/ and TB/ are compiled into library ‘work’. • ghdl -a --work=lib1 LIB1/*.vhd ghdl -a --work=work RTL/*.vhd ghdl -a --work=work TB/*.vhd – Elaboration of design and test bench : command given below will create the executable with ‘full_adder_tb’ name. • ghdl -e --work=work full_adder_tb – Runing simulation: command given below is used to run executable for 1 ms and dump simulation results into file output.vcd. • ghdl -r full_adder_tb --stop-time=1ms --vcd=full_adder.vcd – To observe waveform use following command. • gtkwave full_adder.vcd EE705/707 Lecture No. 22 Prof. Maryam Shojaei Baghini

IIT Bombay Simulation Results EE705/707 Lecture No. 22 Prof. Maryam Shojaei Baghini

IIT Bombay REFERENCES 1. GHDL - User Manual. 2. VHDL Programming by Example 4th Ed - Douglas Perry. EE705/707 Lecture No. 22 Prof. Maryam Shojaei Baghini

IIT Bombay Thank you EE705/707 Lecture No. 22 Prof. Maryam Shojaei Baghini