III-V Channel Transistors Jess A. del Alamo Professor Microsystems - PowerPoint PPT Presentation

III-V Channel Transistors Jesús A. del Alamo Professor Microsystems Technology Laboratories MIT Acknowledgements: • Students and collaborators: D. Antoniadis, J. Lin, W. Lu, A. Vardi, X. Zhao • Sponsors: Applied Materials, DTRA, KIST, Lam Research, Northrop Grumman, NSF, Samsung • Labs at MIT: MTL, EBL 24 April 2017

Moore’s Law at 50: the end in sight? 2

Moore’s Law Moore’s Law = exponential increase in transistor density 2016: Intel 22-core Xeon Broadwell-E5 7.2B transistors Intel microprocessors 3

Moore’s Law How far can Si support Moore’s Law? ? 4

Transistor scaling  Voltage scaling  Performance suffers Supply voltage: Transistor current density: Intel microprocessors Intel microprocessors Goals: • Reduced footprint with moderate short-channel effects • High performance at low voltage 5

Moore’s Law: it’s all about MOSFET scaling 1. New device structures with improved scalability: 2. New materials with improved transport characteristics: n-channel: Si  Strained Si  SiGe  InGaAs p-channel: Si  Strained Si  SiGe  Ge  InGaSb 6

III-V electronics in your pocket! 7

Contents 8

1. Self-aligned Planar InGaAs MOSFETs dry-etched recess selective MOCVD W Mo Lin, IEDM 2012, 2013, 2014 Lee, EDL 2014; Huang, IEDM 2014 implanted Si + selective epi reacted NiInAs Sun, IEDM 2013, 2014 Chang, IEDM 2013 9

Self-aligned Planar InGaAs MOSFETs @ MIT W Mo Lin, IEDM 2012, 2013, 2014 1.0 V gs -V t = 0.5 V L g =20 nm R on =224  m 0.8 0.4 V I d (mA/  m) Recess-gate process: 0.6 • CMOS-compatible 0.4 0.2 • Refractory ohmic contacts 0.0 • Extensive use of RIE 0.0 0.1 0.2 0.3 0.4 0.5 V ds (V) 10

Fabrication process Mo/W ohmic contact CF 4 :O 2 isotropic RIE SF 6 , CF 4 anisotropic RIE + SiO 2 hardmask Resist SiO 2 W/Mo n + InGaAs/InP InP InGaAs/InAs  -Si InAlAs Waldron, IEDM 2007 Digital etch Finished device Cl 2 :N 2 anisotropic RIE O 2 plasma H 2 SO 4 Pad Mo HfO 2 Lin, EDL 2014 • Ohmic contact first, gate last • Precise control of vertical (~1 nm), lateral (~5 nm) dimensions • MOS interface exposed late in process 11

Highest performance InGaAs MOSFET • Channel: In 0.7 Ga 0.3 As/InAs/In 0.7 Ga 0.3 As (t ch =9 nm) • Gate oxide: HfO 2 (2.5 nm, EOT~ 0.5 nm) 3.45 mS/  m Exceeds best HEMT! L g =70 nm: • Record g m,max = 3.45 mS/µm at V ds = 0.5 V • R on = 190 Ω.µm Lin, EDL 2016 12

Excess OFF-state current Transistor fails to turn off: L g =500 nm -5 10 V ds ↑ I d (A/  m) -7 10 -9 10 V ds =0.3~0.7 V step=50 mV -11 10 -0.6 -0.4 -0.2 0.0 V gs (V) OFF-state current enhanced with V ds  Band-to-Band Tunneling (BTBT) or Gate-Induced Drain Leakage (GIDL) Lin, IEDM 2013 13

Excess OFF-state current L g =500 nm -5 10 -4 10 T=200 K V ds ↑ V ds =0.7 V -5 I d (A/  m) 10 -7 10 I d (A/  m) -6 10 L g =80 nm -9 10 -7 10 120 nm V ds =0.3~0.7 V 280 nm step=50 mV -8 10 -11 10 500 nm -0.6 -0.4 -0.2 0.0 V gs (V) -0.6 -0.4 -0.2 0.0 V gs -V t (V) Simulations W/ BTBT+BJT w/ BTBT+BJT -5 10 W/O BTBT w/o BTBT+BJT Lin, EDL 2014 L g =500 nm I d (A/  m) Lin, TED 2015 -7 10 -9 10 L g ↓  OFF-state current ↑ V ds =0.3~0.7 V  bipolar gain effect due to floating body step=50 mV -11 10 -0.4 -0.2 0.0 0.2 V gs (V) 14

2. InGaAs FinFETs Intel Si Trigate MOSFETs 15

Bottom-up InGaAs FinFETs Aspect-Ratio Trapping Fiorenza, ECST 2010 Si Epi-grown fin inside trench Waldron, VLSI Tech 2014 16

Top-down InGaAs FinFETs dry-etched fins Radosavljevic, IEDM 2010 60 nm Kim, IEDM 2013 17

FinFET benchmarking g m normalized by width of gate periphery Natarajan, 2.0 0.18 IEDM 2014 Si FinFETs 5.3 0.23 1.8 4.3 0.57 1.5 1 0.66 g m [mS/  m] 1.0 channel 0.63 aspect 0.6 0.5 0.8 ratio 1 InGaAs FinFETs 0.0 0 20 40 60 W f [nm] • State-of-the-art Si FinFETs: W f =7 nm 18

FinFET benchmarking g m normalized by width of gate periphery Natarajan, 2.0 Radosavljevic, 0.18 IEDM 2014 Si FinFETs IEDM 2011 5.3 0.23 1.8 4.3 0.57 1.5 channel 1 0.66 Kim, IEDM 2013 aspect g m [mS/  m] ratio 1.0 0.63 0.6 0.5 0.8 1 InGaAs FinFETs 0.0 0 20 40 60 Oxland, EDL 2016 Thathachary, W f [nm] VLSI 2015 • Narrowest InGaAs FinFET fin: W f =15 nm • Best channel aspect ratio of InGaAs FinFET: 1.8 • g m much lower than planar InGaAs MOSFETs 19

InGaAs FinFETs @ MIT Key enabling technologies: BCl 3 /SiCl 4 /Ar RIE + digital etch Vardi, • Sub-10 nm fin width DRC 2014, • Aspect ratio > 20 EDL 2015, • Vertical sidewalls IEDM 2015 20

InGaAs FinFETs @ MIT Mo Mo High‐K HSQ SiO 2 HSQ L g W/Mo High‐K n + ‐InGaAs InP InGaAs InGaAs δ ‐ Si InAlAs InP Vardi, VLSI Tech 2016 Vardi, EDL 2016 • CMOS compatible process • Mo contact-first process • Fin etch mask left in place  double-gate MOSFET 21

Most aggressively scaled FinFET W f =7 nm, L g =30 nm, H c =40 nm (AR=5.7), EOT=0.6 nm: 1E-3 1E-4 V DS =500 mV 500 V GS =-0.5 to 0.75 V DS =50 mV 1E-5  V GS =0.25 V DIBL=90 mV/V I d [A/  m] 400 S sat =100 mV/dev 1E-6 I d [  A/  m] 300 1E-7 200 1E-8 100 1E-9 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0 V GS [V] 0.0 0.1 0.2 0.3 0.4 0.5 g m max =900  S/  m V DS [V] 1000 Current normalized by 2xH c 800 V DS =0.5 V g m [  S/  m] 600 At V DS =0.5 V: • g m =900 µS/µm 400 • R on =320 Ω.µm 200 • S sat =100 mV/dec 0 -0.4 -0.2 0.0 0.2 0.4 Vardi, EDL 2016 V GS [V] 22

L g and EOT scaling 1600 250 A: Al 2 O 3 , EOT=2.8 nm 1400 V DS =0.5 V B:Al 2 O 3 /HfO 2 , EOT=1 nm 200 1200 W f  20-22 nm C: HfO 2 , EOT=0.6 nm EOT  1000 S sat [mV/dec] 150 g m [  S/  m] 800 600 100 400 50 200 60 mV/dec EOT  0 0 0 100 200 300 400 500 600 700 0 100 200 300 400 500 600 700 L g [nm] L g [nm] 0.4 350 I off =100 nA/  m 300 0.2 EOT  V DS =0.5 V 250 0.0 200 I on [  A/  m] V T [V] -0.2 150 100 -0.4 EOT  50 -0.6 0 0 100 200 300 400 500 600 700 0 100 200 300 400 500 600 700 L g [nm] L g [nm] Classical scaling with L g and EOT 23

Fin width scaling (EOT=0.6 nm) Contaminated by 150 1600 gate leakage 1400 1200 100 1000 S sat,min [mV/dec] g m max [  S/  m] 800 W f =22  nm 600  W f = 5 nm 50 W f =7 nm 60 mV/dec 400 W f =12 nm 200 W f =17 nm 0  W f =22 nm 0 0 100 200 300 400 500 600 100 1000 L g [nm] L g [nm]  2500 0.3 7 nm  W f = 5 nm 0.2 2000 12 0.1 1500 R on [  m] 0.0 V T [V] 17 W f =22 nm 1000 -0.1 -0.2 500 W f =22 nm -0.3 0 0 50 100 150 200 250 300 0 100 200 300 L g [nm] L g [nm] • Non-ideal fin width scaling • High D it (~5x10 12 cm -2 .eV -1 ); mobility degradation; line edge roughness 24

InGaAs FinFETs: g m benchmarking g m normalized by width of gate periphery: 2.0 W f 0.18 Si FinFETs 5.3 0.23 1.8 4.3 0.57 H c 1.5 H c 1 0.66 2.31.8 g m [mS/  m] 3.3 1.0 5.7 0.63 0.6 0.5 0.8 1 InGaAs FinFETs Double gate Trigate 0.0 0 20 40 60 W f [nm] • First InGaAs FinFETs with W f <10 nm • Record results for InGaAs FinFETs with W f < 25 nm • Still short of Si FinFETs (though they operate at V DD =0.8 V) 25

InGaAs FinFETs: g m benchmarking g m normalized by fin width (FOM for density): 20 W f W f 5.3 Si FinFETs (V DD =0.8 V) 15 H c H c 4.3 g m /W f [mS/  m] 10 5.7 InGaAs FinFETs 1.8 3.3 5 1 0.18 0.66 2.31.8 0.23 1 0.57 0.63 0.6 0.8 0 Vardi, EDL 2016 0 20 40 60 W f [nm] Doubled g m /W f over earlier InGaAs FinFETs 26

Impact of fin width on V T InGaAs doped-channel FinFETs: 50 nm thick, N D ~10 18 cm -3 Vardi, IEDM 2015 T=90K • Strong V T sensitivity for W f < 10 nm; much worse than Si • Due to quantum effects • Big concern for future manufacturing 27

3. Vertical nanowire MOSFET: ultimate scalable transistor L c L spacer L g Vertical NW MOSFET:  uncouples footprint scaling from L g , L spacer , and L c scaling 28

Vertical nanowire MOSFET for 5 nm node 5 nm node Yakimets, TED 2015 Bao, ESSDERC 2014 30% area reduction in 6T‐SRAM 19% area reduction in 32 bit multiplier Vertical NW:  power, performance and area gains w.r.t. Lateral NW or FinFET 29

InGaAs Vertical Nanowires on Si by direct growth Au seed InAs NWs on Si by SAE Selective-Area Epitaxy Vapor-Solid-Liquid (VLS) Technique Riel, MRS Bull 2014 Björk, JCG 2012 30

InGaAs VNW MOSFETs by top-down approach @ MIT Key enabling technologies: 15 nm • RIE = BCl 3 /SiCl 4 /Ar chemistry • Digital Etch (DE) = O 2 plasma oxidation H 2 SO 4 oxide removal 240 nm • Sub-20 nm NW diameter • Aspect ratio > 10 • Smooth sidewalls Zhao, EDL 2014 31

InGaAs VNW Mechanical Stability for D<10 nm Difficult to reach 10 nm VNW diameter due to breakage 8 nm InGaAs VNWs: Yield = 0% Broken NW 32

InGaAs VNW Mechanical Stability for D<10 nm Difficult to reach 10 nm VNW diameter due to breakage 8 nm InGaAs VNWs: Yield = 0% Water-based acid is problem: Broken NW Surface tension (mN/m): • Water: 72 • Methanol: 22 • IPA: 23 Solution: alcohol-based digital etch 33