From Simulink to NoC-based MPSoC on FPGA Simulink front-end for the NoC System Generator (NSG) Francesco Robino KTH Royal Institute of Technology ICES seminar F. Robino (KTH) From Simulink to MPSoC on FPGA 20-05-2014 1 / 17
Overview of the talk Motivation What is the problem? Our goal Reaching the goal Simulink simulation semantics The HeartBeat (HB) model in a MPSoC generated by NSG Connecting Simulink and HB NoC-based MPSoC semantics Experimental evidences and results Conclusion F. Robino (KTH) From Simulink to MPSoC on FPGA 20-05-2014 2 / 17
The problem Matlab/Simulink is today’s de-facto standard for model-based design in domains such as control engineering and signal processing. NoC-based MPSoCs are promising candidates for future embedded system (potentially high performances, low power consumption,. . . ). Synthesis of a Simulink model onto NoC-based MPSoCs is still an open issue. Application Instance P e P e P e P P P e e e Platform Instance F. Robino (KTH) From Simulink to MPSoC on FPGA 20-05-2014 3 / 17
Our goal To enable an end-to-end design flow, we follow the principles of the platform-based design methodology, constraining platform (MPSoC) and functionality (Simulink model) to share a common semantic domain. Application Instance Common semantics domain P e P e P e P e P e P e Platform Instance F. Robino (KTH) From Simulink to MPSoC on FPGA 20-05-2014 4 / 17
Simulink: an environment for system-level design A Simulink model is graphically described through the use of blocks (e.g. an adder, a transfer function, etc.) and subsystems (a set of blocks), linked by signals . Using different blocks and subsystems, architecture and application specification can be combined in a mixed HW/SW model. F. Robino (KTH) From Simulink to MPSoC on FPGA 20-05-2014 5 / 17
Solvers and Simulink simulation semantics Start simulation Simulink simulates a dynamic system by Initialization computing its states at successive time steps over a specified time span, using Store inputs Simulation loop information provided by the model. Compute outputs A solver determines the time of the next Generate outputs simulation step and applies a numerical Advance simulation time method to solve the set of ordinary differential equations (ODEs) that represent N the model. Simulation stop time? Different solvers embody different approaches Y to solve a model. Stop simulation F. Robino (KTH) From Simulink to MPSoC on FPGA 20-05-2014 6 / 17
Solvers and Simulink simulation semantics Solvers: fixed-step VS variable-step Start simulation S0 S0 S1 S2 S3 S3 S4 S4 Initialization 0 0.25 0.5 0.75 1 1.25 1.5 1.75 S0 S1 S2 S3 S4 Store inputs 0 0.5 0.75 1 1.5 Simulation loop Compute outputs discrete VS continuous Generate outputs Continuous: compute model’s continuous states at the current time from the states at Advance simulation time previous time steps and the state derivatives (requires ordinary differential equations). N Simulation one-step VS multi-step stop time? One-step solvers estimate y ( t n ) using only the Y solution at the preceding time point y ( t n − 1 ) Stop simulation Multistep solvers use the results at several preceding time steps to compute the solution F. Robino (KTH) From Simulink to MPSoC on FPGA 20-05-2014 7 / 17
Solvers and Simulink simulation semantics Start simulation Initialization Our approach today targets the following solver Store inputs configuration: Simulation loop Compute outputs fixed-step (constant step size t step ) Generate outputs discrete Advance simulation time one-step However, it can be extended to other solvers too. . . N Simulation stop time? Y Stop simulation F. Robino (KTH) From Simulink to MPSoC on FPGA 20-05-2014 8 / 17
Simulink Embedded Coder Begin When we select a fixed-step solver, we can use the Simulink Embedded Coder to generate C code of Initialize SW processes the model for use on embedded processors. The Wait first interrupt code generated include: Execute rt_onestep Main scheduler sensitive on interrupt. rt onestep function, implemented in the interrupt service routine (ISR), describing the N Interrupt received? functionality of the system. Y The generated software is compliant with the execution model of the Simulink simulation! SW Interrupt PE F. Robino (KTH) From Simulink to MPSoC on FPGA 20-05-2014 9 / 17
The HeartBeat model in a MPSoC generated by NSG S i m u l i n k m o d e l Begin process network Initialize SW processes and system specs Wait first HB tick N o C S y s t e m G e n e r a t o r H B p r o c e s s w r a p p e r Execute SW processes H B t i c k s H B p e r i o d 3 5 8 7 6 N HB tick ε ε PE 0 PE 1 received? c c NoC NoC P E 0 P E 1 0 1 2 3 0 1 2 3 Y HB tick SW 9 8 P E 3 P E 2 PE ε ε PE 3 PE 2 c c NoC NoC 4 0 1 2 3 5 0 1 2 3 4 F. Robino (KTH) From Simulink to MPSoC on FPGA 20-05-2014 10 / 17
Connecting Simulink and HB NoC-based MPSoC semantics Simulink Emb. Coder HeartBeat Start simulation Begin Begin Initialization Initialize SW processes Initialize SW processes Store inputs Wait first interrupt Wait first HB tick Simulation loop Compute outputs Execute rt_onestep Execute SW processes Generate outputs Advance simulation time N N HB tick Interrupt received? received? N Simulation Y Y stop time? HB tick S W S W Y Interrupt Stop simulation P E P E Table: Common semantics parameters and design rules Application Instance Simulink HB compliant MPSoC time steps HB ticks step size ( t step ) HB period ( t HB ) simulation loop SW processes triggered by HB wrapper rt onestep SW running on one PE blocks instructions of SW process subsystem SW processes on a single PE (rt onestep) signal NoC communication path Platform Instance F. Robino (KTH) From Simulink to MPSoC on FPGA 20-05-2014 11 / 17
Case study: DSP system (Digital FIR filter) http://www.mathworks.se/help/dsp/ug/digital-filter-block.html F. Robino (KTH) From Simulink to MPSoC on FPGA 20-05-2014 12 / 17
Case study: Embedded coder vs SLD HB methodology P E 0 P E 1 P E 0 P E 3 P E 2 F. Robino (KTH) From Simulink to MPSoC on FPGA 20-05-2014 13 / 17
Case study: results Table: WCET, minimum t HB , memory requirements 1 PE 4 PEs Source Noise Filter Sink WCET - Min. t HB [ms] 28 7,90 11,68 8,00 0,01 Mem. req. w/o OS [KB] 53 33 27 21 16 Mem. req. eCos [KB] +20 +20 for each PE Mem. req. uCLinux [MB] +2 +2 for each PE Splitting the system in 4 subsystems using this methodology, increases the throughput of the system of ca 2 . 4 × . If we would have created 4 subsystems having equal WCET (i.e. 7 ms), we could have reached a theoretical 4 × throughput increase. The increase in throughput comes at the expense of memory. F. Robino (KTH) From Simulink to MPSoC on FPGA 20-05-2014 14 / 17
Case study: semantics preserving? [0.00003,0.00006, -0.001011,-0.006998,...] [X,-0.014091, [0.000000,0.453990, 0.043682,0.440711,...] 0.809017,0.987688,...] [X,X, 0.00003,0.00006,...] [0.043682,0.440711,...] [0.809017,0.987688,...] [0.00003,0.00006,...] F. Robino (KTH) From Simulink to MPSoC on FPGA 20-05-2014 15 / 17
Conclusions We have described a system-level design flow that allows the synthesis of Simulink models to NoC-based MPSoCs , generating a working prototype on low-cost FPGAs. The generated MPSoC is constrained to share a common semantics domain with the Simulink model, so that the results between simulation and implementation of the prototype are the same, without the need of resource consuming SW components (such as OS). Design methodology based on process constructors — HB process wrappers to provide execution semantics to the MPSoC. Developed a synthesis methodology with similarities with synchronous HW design Minimize HB period t HB . Exploits task, data and pipeline parallelism. F. Robino (KTH) From Simulink to MPSoC on FPGA 20-05-2014 16 / 17
Questions? Suggestions: Can this approach be extended to other Simulink solvers? Does this approach provide real-time guarantees? No OS overhead Quite precise measurement of WCET When no shared connections, quite precise (and not pessimistic) WCCT Why not everything asynchronous 1 ? (see asynchronous CPUs) 1 Asynchronous circuits are not governed by a global clock, but they use signals to indicate completion of instructions and operations, specified by data transfer protocols. F. Robino (KTH) From Simulink to MPSoC on FPGA 20-05-2014 17 / 17
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